Reset And Supply Management; Power Supply Schemes; Power Supply Supervisor - ST STM32L15 QC Series Datasheet

STM32L151xC/C-A STM32L152xC/C-A
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded Arm core, the STM32L151xC/C-A and STM32L152xC/C-A devices
are compatible with all Arm tools and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L151xC/C-A and STM32L152xC/C-A devices embed a nested
vectored interrupt controller able to handle up to 56 maskable interrupt channels (not
including the 16 interrupt lines of Arm
• Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
•
Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
•
Support for tail-chaining
• Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3

Reset and supply management

3.3.1

Power supply schemes

•
V
DD
externally through V
•
V
SSA
and PLL (minimum voltage to be applied to V
and V
3.3.2

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
•
The other version without BOR operates between 1.65 V and 3.6 V.
After the V
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the V
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up must guarantee that 1.65 V is reached on V
POR area.
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
pins.
DD
, V = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
DDA
must be connected to V
SSA
threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
DD
® ®
Cortex -M3) and 16 priority levels.
DDA
and V , respectively.
DD SS
DS10262 Rev 8
Functional overview
is 1.8 V when the ADC is used). V
min value becomes
DD
at least 1 ms after it exits the
DD
DDA
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