Table 53. I2S Characteristics - ST STM32L15 QC Series Datasheet

Electrical characteristics
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification -
Chapter 7 (version 2.0).
I2S characteristics
Symbol
f
MCK
f
CK
D
CK
t
r(CK)
t
f(CK)
t
v(WS)
t
h(WS)
t
su(WS)
t
h(WS)
t
su(SD_MR)
t
su(SD_SR)
t
h(SD_MR)
t
h(SD_SR)
t
v(SD_ST)
t
h(SD_ST)
t
v(SD_MT)
t
h(SD_MT)
1. The maximum for 256xFs is 8 MHz
Note: Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), f
behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
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Table 53. I2S characteristics

Parameter
I2S Main Clock Output
I2S clock frequency
I2S clock frequency duty cycle Slave receiver, 48KHz
I2S clock rise time
I2S clock fall time
WS valid time
WS hold time
WS setup time
WS hold time
Data input setup time
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
, f and D
MCK CK CK
DS10262 Rev 8
STM32L151xC/C-A STM32L152xC/C-A
Conditions
-
Master data: 32 bits
Slave data: 32 bits
Capacitive load CL=30pF
Master mode
Master mode
Slave mode
Slave mode
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
values. These values reflect only the digital peripheral
Min Max Unit
(1)
256 x 8K 256xFs MHz
- 64xFs
MHz
- 64xFs
30 70
8
-
8
4 24
0 -
15 -
0 -
8 -
9 -
5 -
4 -
- 64
22 -
- 12
8 -
%
ns