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AN5673
Application note
Getting started with STM32C0 Series hardware development
Introduction
This document is addressed to system designers who require an overview of the hardware implementation of development
board features (such as power supply, clock management, reset control, boot mode settings and debug management). It shows
how to use
STM32C0 Series
devices and describes the minimum hardware resources required to develop an application.
This document also includes detailed reference design schematics with the description of the main components, interfaces and
modes.
AN5673 - Rev 2 - December 2022
www.st.com
For further information contact your local STMicroelectronics sales office.
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Table of Contents
Related Manuals for ST STM32C0 Series
Summary of Contents for ST STM32C0 Series
- Page 1 AN5673 Application note Getting started with STM32C0 Series hardware development Introduction This document is addressed to system designers who require an overview of the hardware implementation of development board features (such as power supply, clock management, reset control, boot mode settings and debug management). It shows...
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Page 2: Power Supplies And Reset Sources
Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. Power supplies The STM32C0 series devices require a 2.0 to 3.6 V operating supply voltage (V ). Several different power supplies are provided to specific peripherals: •... -
Page 3: Figure 1. Stm32C0 Series Power Supply
AN5673 Power supplies Figure 1. STM32C0 series power supply CORE VDD/VDDA Regulator DDIO Kernel logic (CPU, digital and 1 x 100 nF GPIOs logic memories) + 1 x 4.7 µF VREF+ VREF+ 100 nF VSS/VSSA (1): Internally connected to the V pin on packages without VREF+ pin. -
Page 4: Power Supply Supervisor
For more details on the brown-out reset thresholds, refer to the electrical characteristics section in the corresponding datasheet. Reset This section describes the three types of reset on microcontrollers of the STM32C0 series, namely power reset, system reset and RTC domain reset. AN5673 - Rev 2... -
Page 5: Power Reset
AN5673 Reset 1.3.1 Power reset A power reset is generated when one of the following events occurs: • power-on reset (POR) or brown-out reset (BOR) • exit from Standby mode • exit from Shutdown mode Power and brown-out reset set all registers to their reset values. When exiting Standby mode, all registers in the V domain are set to their reset value. -
Page 6: Figure 3. Simplified Diagram Of The Reset Circuit
AN5673 Reset Figure 3. Simplified diagram of the reset circuit System reset External Filter reset NRST Internal Pulse reset sources generator (min 20 μs) Bidirectional reset Reset holder CLEAR Note: Upon power reset or wake up from shutdown mode, the NRST pin is configured as Reset input/output and driven low by the system until it is reconfigured to the expected mode when the option bytes are loaded, in the fourth clock cycle after the end of t rstempo... -
Page 7: Rtc Domain Reset
AN5673 Reset 1.3.3 RTC domain reset The RTC domain has two specific resets. An RTC domain reset is generated when one of the following events occurs: • software reset, triggered by setting the RTCRST bit in the register RCC_CSR1 • power on An RTC domain reset only affects the LSE oscillator, the RTC, and the register RCC_CSR1. -
Page 8: Clocks
AN5673 Clocks Clocks The microcontrollers of the STM32C0 series provide the following clock sources producing primary clocks: • HSI48 RC, a high-speed fully integrated RC oscillator producing HSI48 clock (48 MHz) • HSE OSC, a high-speed oscillator with external crystal/ceramic resonator or external clock source, producing HSE clock (4 to 48 MHz) •... -
Page 9: Figure 4. Clock Tree
AN5673 Clocks • RTC, with these clock sources to select from: – – – HSE clock divided by 32 The functionality in Stop mode (including wake-up) is supported only when the clock is LSI or LSE. • IWDG, always clocked with LSI clock. ®... -
Page 10: Hse Clock
AN5673 HSE clock HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE user external clock The resonator and the load capacitors must be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. -
Page 11: Hsi48 Clock
AN5673 HSI48 clock HSI48 clock The HSI48 clock signal is generated from an internal 48 MHz RC oscillator. The HSI48 RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a startup time faster than the HSE crystal oscillator. However, even after calibration, it is less accurate than an oscillator using a frequency reference such as quartz crystal or ceramic resonator. -
Page 12: System Clock (Sysclk) Selection
AN5673 System clock (SYSCLK) selection System clock (SYSCLK) selection One of the following clocks can be selected as system clock (SYSCLK): • • • HSISYS • The maximum frequency of the system clock is 48 MHz. Upon system reset, the HSISYS clock derived from the HSI48 oscillator is selected as system clock. -
Page 13: Adc Clock
AN5673 ADC clock ADC clock The ADC clock (refer to the device datasheet for maximum frequency) is derived from the system clock or from the kernel clock output. It can be prescaled by 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128 or 256, by configuring the ADC1_CCR register. -
Page 14: Internal / External Clock Measurement With Tim14 / Tim16 / Tim17
AN5673 Internal / external clock measurement with TIM14 / TIM16 / TIM17 2.13 Internal / external clock measurement with TIM14 / TIM16 / TIM17 It is possible to indirectly measure the frequency of all on-board clock sources with the TIM14, TIM16, and TIM17 channel 1 input capture, as shown in the figures in each of the corresponding subsections. -
Page 15: Figure 7. Frequency Measurement With Tim16 In Capture Mode
AN5673 Internal / external clock measurement with TIM14 / TIM16 / TIM17 Figure 7. Frequency measurement with TIM16 in capture mode TIM 16 TI1SEL[3:0] GPIO MCO2 TIM17 By setting the TI1SEL[3:0] field of the TIM17_TISEL register, the clock selected for the input capture channel1 of TIM17 can be one of the following: •... -
Page 16: Peripheral Clock Enable Registers
AN5673 Peripheral clock enable registers To further improve the precision of the HSI48 oscillator calibration, it is advised to employ one, or a combination of the following measures, to increase the frequency measurement accuracy: • set the HSISYS divider to 1 for HSISYS frequency to be equal to HSI48 frequency, •... -
Page 17: Boot Configuration
AN5673 Boot configuration Boot configuration Three different boot modes can be selected through the BOOT0 pin, the BOOT_LOCK bit in the FLASH_SECR register, and the boot configuration bits nBOOT1, BOOT_SEL, and nBOOT0 in the user option byte, as shown in the following table. - Page 18 AN5673 Boot configuration Physical remap Once the boot mode is selected, the application software can modify the memory accessible in the code area. This modification is performed by programming the MEM_MODE bits in the SYSCFG configuration register 1 (SYSCFG_CFGR1). Embedded bootloader The embedded bootloader is located in the system memory, programmed by STMicroelectronics during production.
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Page 19: Debug Management
2-pin (clock + data) interface to the debug access port. Pinout and debug port pins The microcontrollers of the STM32C0 series are offered in packages with varying numbers of pins. 4.3.1 Serial wire debug (SWD) pin assignment The same SWD pin assignment is available on all STM32C0 Series packages. -
Page 20: Internal Pull-Up And Pull-Down On Swd Pins
AN5673 Pinout and debug port pins 4.3.2 Internal pull-up and pull-down on SWD pins Once the SWD I/O is released by the user software, the GPIO controller takes control of these pins. The reset states of the GPIO control registers put the I/Os in the equivalent states: •... - Page 21 AN5673 Pinout and debug port pins The multi bonding approach offers not only more versatility for the product configuration, but also offers an extended drive strength on the multi bonded pads. By configuring multiple devices pad in output mode (with the same output level), the transistor drive resistance is decreased and consequently the voltage drop (V and V at the device pin is reduced.
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Page 22: Recommendations
AN5673 Recommendations Recommendations Printed circuit board For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to ground (V ) and another dedicated to the V supply. This provides good decoupling and a good shielding effect. -
Page 23: Other Signals
AN5673 Other signals Other signals When designing an application, the EMC performance can be improved by closely studying: • Signals for which a temporary disturbance affects the running process permanently. Such as interrupts and handshaking strobe signals, but not LED commands. For these signals, a surrounding ground trace, shorter lengths, and the absence of noisy and sensitive traces nearby (crosstalk effect) improve the EMC performance. -
Page 24: Reference Design
The reference design shown in the figure below is based on STM32C031, a highly integrated microcontroller ® running at 48 MHz, combining the Cortex -M0+ 32-bit RISC CPU core with 32 Kbytes of embedded flash memory and 12 Kbytes of SRAM. Figure 13. STM32C0 series reference schematic PA15 PB12 PB11 PB10 RESET C4 = 100 nF R1 = 390 Ω... -
Page 25: Clock
Section 1.3 Reset. Note: By default the reset holder is activated on STM32C0 series devices. Any internal reset results in pulling down NRST pin until it reaches its V threshold, ensuring that the capacity on this line is fully discharged. -
Page 26: Component References
AN5673 Component references Component references Table 4. Mandatory components Component Reference Value Quantity Comments Microcontroller STM32C031CxT 48-pin package Capacitor 100 nF Ceramic capacitors (for decoupling) Capacitor 4.7 μF Used for VDD Table 5. Optional components Component Reference Value Quantity Comments Used for HSE, the value depends on Resistor 390 Ω... -
Page 27: Revision History
Document revision history Date Version Changes 06-Jun-2022 Initial release. • Updated the Table 1. Power supplies of STM32C0 series Updated the Figure 1. STM32C0 series power supply Updated the Section 2 Clocks 14-Dec-2022 Updated the Figure 4. Clock tree •... -
Page 28: Table Of Contents
AN5673 Contents Contents Power supplies and reset sources ..........2 Power supplies . - Page 29 AN5673 Contents Component position ............22 Ground and power supply (V ) .
- Page 30 Power supplies of STM32C0 series ........
- Page 31 STM32C0 series reference schematic ........
- Page 32 ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’...
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