Figure 23. Spi Timing Diagram - Master Mode - ST STM32L15 QC Series Datasheet

Electrical characteristics
High
NSS input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t su(MI)
MISO
INP UT
MOSI
OUTPUT
1. Measurement points are done at CMOS levels: 0.3V
98/134

Figure 23. SPI timing diagram - master mode

t c(SCK)
t w(SCKH)
t w(SCKL)
MSB IN
t h(MI)
MSB OUT
t v(MO)
and 0.7V
DD
DS10262 Rev 8
STM32L151xC/C-A STM32L152xC/C-A
(1)
BIT6 IN
B I T1 OUT
t h(MO)
DD.
t r(SCK)
t f(SCK)
LSB IN
LSB OUT
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