Supermicro X13DEG-M User Manual page 63

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DDR5 Memory Population Table for HMB CPU 32-DIMM Motherboards
1 CPU:
Memory Population Sequence
1 CPU & 1 DIMM
P1-DIMMA1 or P1-DIMME1
P1-DIMMA1 / P1-DIMMG1
1 CPU & 2 DIMMs
or P1-DIMMC1 / P1-DIMME1
1 CPU & 4 DIMMs
P1-DIMMA1 / P1-DIMMC1 / P1-DIMME1 / P1-DIMMG1
1 CPU & 8 DIMMs
P1-DIMMA1/P1-DIMMB1 / P1-DIMMC1 / P1-DIMMD1 / P1-DIMME1 / P1-DIMMF1 / P1-DIMMG1 / P1-DIMMH1
P1-DIMMA1 / P1-DIMMA2 / P1-DIMMB1 / P1-DIMMB2 / P1-DIMMC1 / P1-DIMMC2 / P1-DIMMD1 / P1-DIMMD2 /
1 CPU & 16 DIMMs
P1-DIMME1 / P1-DIMME2 / P1-DIMMF1 / P1-DIMMF2 / P1-DIMMG1 / P1-DIMMG2 / P1-DIMMH1 / P1-DIMMH2
2 CPUs:
Memory Population Sequence
(Recommended)
CPU1: P1-DIMMA1, CPU2: P2-DIMMA1
2 CPUs & 2 DIMMs
or CPU1: P1-DIMME1, CPU2: P2-DIMME1
CPU1: P1-DIMMA1 / P1-DIMMG1, CPU2: P2-DIMMA1 / P2-DIMMG1
2 CPUs & 4 DIMMs
or CPU1: P1-DIMMC1 / P1-DIMME1, CPU2: P2-DIMMC1 / P2-DIMME1
CPU1: P1-DIMMA1 / P1-DIMMC1 / P1-DIMME1 / P1-DIMMG1
2 CPUs & 8 DIMMs
or CPU2: P2-DIMMA1 / P2-DIMMC1 / P2-DIMME1 / P2-DIMMG1
CPU1: P1-DIMMA1 / P1-DIMMB1 / P1-DIMMC1 / P1-DIMMD1 / P1-DIMME1 / P1-DIMMF1 / P1-DIMMG1 / P1-DIMMH1
2 CPUs & 16 DIMMs
or CPU2: P2-DIMMA1 / P2-DIMMB1 / P2-DIMMC1 / P2-DIMMD1 / P2-DIMME1 / P2-DIMMF1 / P2-DIMMG1 / P2-DIMMH1
CPU1: P1-DIMMA1 / P1-DIMMA2 / P1-DIMMB1 / P1-DIMMB2 / P1-DIMMC1 / P1-DIMMC2 / P1-DIMMD1 / P1-DIMMD2 /
P1-DIMME1 / P1-DIMME2 / P1-DIMMF1 / P1-DIMMF2 / P1-DIMMG1 / P1-DIMMG2 / P1-DIMMH1 / P1-DIMMH2
2 CPUs & 32 DIMMs
CPU2: P2-DIMMA1 / P2-DIMMA2 / P2-DIMMB1 / P2-DIMMB2 / P2-DIMMC1 / P2-DIMMC2 / P2-DIMMD1 / P2-DIMMD2 /
P2-DIMME1 / P2-DIMME2 / P2-DIMMF1 / P2-DIMMF2 / P2-DIMMG1 / P2-DIMMG2 / P2-DIMMH1 / P2-DIMMH2
Notes:
1. Max Series (HBM) processors support 1DPC (4800 MT/s) / 2DPC (4400 MT/s) to
optimize the memory bandwidth. Max Series (HBM) processors support 1, 2, 4, 8,
or 16 DIMMs in Flat Mode and Cache Mode, and 0 DIMMs in HBM-Only mode.
HBM-Only mode runs exclusively using HBM memory.
2. For the best memory performance in Flat mode and Cache mode, please use 4,
8, or 16 DIMM configurations. (At least one DIMM per memory controller for bal-
anced configuration)
4 DIMMs -> populate 1 DIMM/iMC
8 DIMMs -> populate 1 DIMM/Channel, 2 DIMM/iMC
16 DIMMs -> populate 2 DIMM/Channel, 4 DIMM/iMC
3. All other configurations not listed above are not supported.
4. For 2 Socket design, each socket has to be populated identically.
63
Chapter 2: Installation

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