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Chapter 4: UEFI BIOS
line earlier and then has silently dropped it from its cache without modifying it. If "Stale
AtoS" is enabled, a line will transition to the S state when the line in the A state returns
only snoop misses. That way, subsequent reads to the line will encounter it in the S state
and will not have to snoop, saving the latency and snoop bandwidth. Stale "AtoS" may
be beneficial in a workload where there are many cross-socket reads. The options are
Disable, Enable, and Auto.
LLC Dead Line Alloc
Select Enable to opportunistically fill the dead lines in the LLC. The options are Disable,
Enable, and Auto.
Memory Configuration
This feature allows you to configure the Integrated Memory Controller (iMC) settings.
Enforce DDR Memory Frequency POR
Select POR to enforce Plan of Record (POR) restrictions for DDR memory frequency
and voltage programming. The options are POR and Disable.
Memory Frequency
Use this feature to set the maximum memory frequency for onboard memory modules.
The options are Auto, 3200, 3600, 4000, 4400, 4800, 5200, and 5600. Please note that
the available options are CPU dependent.
Data Scrambling for DDR5
Select Enable to enable data scrambling for DDR5 modules to enhance memory data
security. The options are Disable and Enable.
Enable fADR
Select Enable to have Fast Asynchronous DRAM Refresh (fADR) support to enhance
memory performance on Intel PMem 300 series DIMMs. With the support of fADR fea-
ture, the ADR safe domain (flush domain) includes CPU caches, IIO caches, and Write
Pending Queue (WPQ). The implementation of fADR can lower flush time and reduce
flush times. The support of fADR is based on your motherboard hardware features. The
options are Disable and Enable. Please note that this feature depends on the support
of Intel Optane PMem 300 Series.
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