Supported Gpio Register; Gpio Registers - Advantech PCE-2033 Manual

Lga1700 12th/13th generation intel® core™ i9/i7/i5/i3 & pentium®/celeron® cpu board for ipc-2 series chassis
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B.1

Supported GPIO Register

Provided below are comprehensive descriptions of the GPIO addresses, along with a
sample programming demonstrations.
B.2

GPIO Registers

GPIO 1
CRF0 (GP10-GP17 I/O selection register. Default 0xFF)
When set to '1', the respective GPIO port is programmed as an input port.
When set to '0', the respective GPIO port is programmed as an output port.
CRF1 (GP10-GP17 data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/writ-
ten.
If a port is programmed to be an input port, then its respective bit can only be read.
CRF2 (GP10-GP17 inversion register. Default 0x00)
When set to '1', the incoming/outgoing port value is inverted.
When set to '0', the incoming/outgoing port value is the same as in data register.
GPIO 0
CREC (GP00-GP07 I/O selection register. Default 0xFF)
When set to '1', the respective GPIO port is programmed as an input port.
When set to '0', the respective GPIO port is programmed as an output port.
CRED (GP00-GP07 data register. Default 0xFF)
If a port is programmed to be an output port, then its respective bit can be read/writ-
ten.
If a port is programmed to be an input port, then its respective bit can only be read.
CREE (GP00-GP07 inversion register. Default 0x00)
When set to '1', the incoming/outgoing port value is inverted.
When set to '0', the incoming/outgoing port value is the same as in data register.
Extended Function Index Registers (EFIRs)
The EFIRs are write-only registers with port address 2Eh or 4Eh on PC/AT systems.
Extended Function Data Registers (EFDRs)
The EFDRs are read/write registers with port address 2Fh or 4Fh on PC/AT systems
PCE-2033/2133 User Manual
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