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capacitors on your schematic and PCB.
The following principles of PCIe interface design should be complied with to meet PCIe specification.
⚫
Keep the PCIe data and control signals away from sensitive circuits and signals, such as RF, audio,
crystal, and oscillator signals.
⚫
Add a capacitor in series on Tx/Rx traces to prevent any DC bias.
⚫
Keep the maximum trace length less than 200 mm.
⚫
Keep the length matching of each differential data pair (Tx/Rx) less than 0.7 mm for PCIe routing
traces.
⚫
Keep the differential impedance of PCIe data trace as 85 Ω ±10 %.
⚫
You must not route PCIe data traces under components or cross them with other traces.
⚫
It is recommended to use a push-pull GPIO to output low level that approaches to 0 V rather than
using a pull-down resistor to get low level voltage. Otherwise, voltage division may be formed with
the pull-up resistor integrated inside the module, resulting in an uncertain 0 V voltage that could
furtherly lead to unpredictable problems.
Table 18: PCIe Trace Length Inside the Module
Signal
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_TX_P
PCIE_TX_M
PCIE_RX_P
PCIE_RX_M
RM520N-GL_Hardware_Design
Pin No.
Length (mm)
55
12.068
53
12.0345
43
5.095
41
4.9483
49
12.0239
47
11.9834
5G Module Series
Length Difference (mm)
0.0335
0.1467
0.0405
49 / 84
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