Quectel RM520N-GL Hardware Design page 39

VCC(H)
FULL_CARD_
POWER_OFF#
RESET#
PCIE_CLKREQ_N
Execute AT+CFUN=0,
and the module responds OK
PCIE_RST_N
PCIE_REFCLK
Module Status
NOTE:
1. The timing parameters after the host pulls up FULL_CARD_POWER_OFF# refer to the boot timing of the PCIe
mode module.
2. When the module is in USB mode, please ignore the PCIe related signals and their timing parameters in the figure.
Table 13: Reset Timing of the Module's Hard Reset
Symbol Min.
T -
PERST#-RESET#
T 0 ms
RST#-FCPO#
T 900 ms
FCPO#
T -
FCPO#-CLKREQ#
T 100 ms
FCPO#-PERST#
100 μs
T
REFCLK-PERST#
T -
PERST#-RST#
RM520N-GL_Hardware_Design
T
RST#-FCPO#
T
PERST#-RESET#
Active
Figure 14: Reset Timing of the Module's Hard Reset
Typ. Max.
100 ms -
100 ms -
- -
100 ms -
-
- -
- 390 ms
T
FCPO#
T
FCPO#-CLKREQ#
T
FCPO#-PERST#
Resetting
Comment
Time from host pulling down PCIE_RST_N to
pulling down RESET#.
Time from host pulling down RESET# to pulling
down FULL_CARD_POWER_OFF#.
Module hardware Reset. Ensure that the module
has been powered off completely.
The time when the module requests the PCIe
clock from the host.
The time when the host GPIO controls the
module to exit the PERST# state.
The time period during which REFCLK_P/M is
stable before PCIE_RST_N is inactive.
The time when the host GPIO controls the
module to exit the reset state in advance. For the
host GPIO, the time is the maximum time that is
allowed, while for the module's RESET# pin, it is
the minimum time that is allowed. The time will
continue to be updated.
5G Module Series
3.7 V
V ≥ 1.19 V
IH
1.8 V
T
PERST#-RST#
T
REFCLK-PERST#
Booting
38 / 84