Reference Design For Pcie - Quectel RM520N-GL Hardware Design

41 PCIE_TX_M
50 PCIE_RST_N
52 PCIE_CLKREQ_N
54 PCIE_WAKE_N

4.3.3. Reference Design for PCIe

The following figure shows a reference circuit for the PCIe interface.
Host
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_TX_P
PCIE_TX_M
PCIE_RX_P
PCIE_RX_M
PCIE_WAKE_N
PCIE_CLKREQ_N
PCIE_RST_N
NOTE: The voltage level VCC_IO_HOST of these three signals depend on the host side due to open drain.
To ensure the signal integrity of PCIe interface, AC coupling capacitors C3 and C4 should be placed close
to the host on PCB. C1 and C2 have been integrated inside the module, so do not place these two
12
PCIE_RST_N behaves as DI in PCIe EP mode, and as OD in PCIe RC mode. PCIE_CLKREQ_N and PCIE_WAKE_N
behave as OD in PCIe EP mode, and as DI in PCIe RC mode. PCIe EP mode is configured by default.
RM520N-GL_Hardware_Design
AO PCIe transmit (-)
PCIe reset
12
DI
Active LOW
PCIe clock request
12
OD
Active LOW
PCIe wake up
12
OD
Active LOW
R4 0 Ω
R5 0 Ω
C3 220 nF
C4 220 nF
VCC_IO_HOST
R1 R2 R3
10k 10k 4.7k
R4
NM_10k
Figure 20: PCIe Interface Reference Circuit
of 85 Ω
1.8/3.3 V
1.8/3.3 V
1.8/3.3 V
PCIE_REFCLK_P
55
PCIE_REFCLK_M
53
PCIE_RX_P
49
PCIE_RX_M
47
PCIE_TX_P
43
PCIE_TX_M
41
PCIE_WAKE_N
54
PCIE_CLKREQ_N
52
PCIE_RST_N
50
5G Module Series
Module
C1 220 nF
C2 220 nF
BB
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