Reset - Quectel RM520N-GL Hardware Design

The timing of turning-off scenario is illustrated by the following figure.
VCC(H)
FULL_CARD_
POWER_OFF#

RESET#

PCIE_RST_N
Module Status
NOTE:
When the module is in USB mode, please ignore the PCIe related signals and their timing parameters in the figure.
Figure 10: Turn-off Timing through FULL_CARD_POWER_OFF#
Table 10: Turn-off Timing of the Module through FULL_CARD_POWER_OFF#
Symbol Min.
T -
PERST#-RESET#
T 0 ms
RESET#-FCPO#
T 900 ms
FCPO#
3.6. Reset
RESET# is an active LOW signal (1.8 V logic level). When this pin is active, the module will immediately
enter reset condition.
Please note that triggering the RESET# signal will lead to loss of all data in the module and removal of
system drivers. It will also disconnect the modem from the network.
RM520N-GL_Hardware_Design
3.7 V
≥ 1.19 V
V
IH
1.8 V
Execute AT+CFUN=0,
and the module responds OK
Active
Running
Typ.
100 ms
100 ms
-
T
RESET#-FCPO#
T
PERST#-RESET#
Turn-off procedure
Max. Comment
Time from host pulling down PCIE_RST_N to
-
pulling down RESET#
Time from host pulling down RESET# to
-
pulling down FULL_CARD_POWER_OFF#
Time from the host pulling down the
FULL_CARD_POWER_OFF# to the module
-
shutdown. Ensure that the module has been
powered off completely
5G Module Series
T
FCPO#
V ≤ 0.7 V
IL
OFF
OFF
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