Quectel RM520N-GL Hardware Design page 26

49 PCIE_RX_P
50 PCIE_RST_N
51 GND
52 PCIE_CLKREQ_N
53 PCIE_REFCLK_M
54 PCIE_WAKE_N
55 PCIE_REFCLK_P
10
56 RFFE_CLK *
57 GND
10
58 RFFE_DATA
59 RESERVED
60 N79_TX_EN*
61 RESERVED
11
62 COEX_RXD*
63 RESERVED
11
64 COEX_TXD*
65 RESERVED
66 USIM1_DET
67 RESET#
68 RESERVED
9
PCIE_RST_N behaves as DI in PCIe EP mode, and as OD in PCIe RC mode. PCIE_CLKREQ_N and PCIE_WAKE_N
behave as OD in PCIe EP mode, and as DI in PCIe RC mode. PCIe EP mode is configured by default.
10
If this function is required, please contact Quectel for more details
11
Please note that COEX_RXD and COEX_TXD cannot be used as general UART ports.
RM520N-GL_Hardware_Design
AI PCIe receive (+)
PCIe reset.
9
DI
Active LOW
Ground
PCIe clock request
9
OD
Active LOW
AIO PCIe reference clock (-)
PCIe wake up
9
OD
Active LOW
AIO PCIe reference clock (+)
Used for external MIPI
DO, PD
IC control
Ground
Used for external MIPI
* DIO, PD
IC control
Notification from SDR to
DO WLAN when n79
transmitting
5G/LTE and WLAN
DI, PD
coexistence receive
5G/LTE and WLAN
DO, PD
coexistence transmit
(U)SIM1 card hot-plug
DI, PU
detect
Reset the module.
DI, PU
Active LOW
5G Module Series
1.8/3.3 V
1.8/3.3 V
1.8/3.3 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
Internally pulled
1.8 V
up to 1.8 V
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