Texas Instruments ADS1278V2EVM-PDK User Manual page 6

Hardware
2.3 VCOM Buffer
Figure 2-4 shows the buffer circuit for the ADC VCOM signal. The output of the VCOM buffer connects to the
VOCM signal of the input driver amplifiers. The J1 VCOM header pins (depopulated by default) can also be used
to provide an alternate source for VCOM by depopulating resistor R5. Jumper J1 can also be used to connect
the VCOM signal to an external piece of test equipment to set the common-mode voltage. A common use case
is to connect this signal to the Audio Precision SYS-2722 to set the signal generator's common-mode output.
AVDD
8
V+
C8
25V
0.1 µF
GND
2.4 ADC Connections and Decoupling
The circuit shown in Figure 2-5
connection has a 100nF decoupling capacitor and each power supply has a 10µF decoupling capacitor. These
capacitors are physically close to the device and have a good connection to the GND plane. Also, each digital
input has a 50Ω series resistor. These resistors smooth the edges of the digital signals so that the signals have
minimal overshoot and ringing. Although not strictly required, these components can be included in final designs
to improve digital signal integrity.
AVDD AVDD_ADC
R1
0
C2 C3 C4 C5
25V 25V 25V 25V
0.1 µF 0.1 µF 0.1 µF 0.1 µF
GND
IOVDD IOVDD_ADC
R3
0
6 ADS1278EVM-PDK Evaluation Module
U2C
OPA2320AQDGKRQ1
4
V-
GND
Figure 2-4. VCOM Buffer Circuit
shows all connections to the ADS1278 (U1). Each analog power supply
5
44
53
C1
60
10V DVDD DVDD_ADC
R2
10µF
26
0
C6
22
10V
23
10µF
VCOM_ADC
55
GND
VREFP
56
VREFN 57
3
CHAN_P1
4
CHAN_N1
C7
10V
1
CHAN_P2
10µF
2
CHAN_N2
63
CHAN_P3
GND
64
CHAN_N3
61
CHAN_P4
62
CHAN_N4
51
CHAN_P5
52
CHAN_N5
49
CHAN_P6
50
CHAN_N6
47
CHAN_P7
48
CHAN_N7
45
CHAN_P8
46
CHAN_N8
Figure 2-5. ADS1278 Connections and Decoupling
Copyright © 2024 Texas Instruments Incorporated
U2A
OPA2320AQDGKRQ1
2
1
A
VCOM_ADC
3
C9
25V
0.1 µF
GND
U1
/PWDN1
42
AVDD PWDN1
/PWDN2
41
AVDD PWDN2
/PWDN3
40
AVDD PWDN3
/PWDN4
39
AVDD PWDN4
/PWDN5
38
PWDN5
/PWDN6
37
DVDD PWDN6
36 /PWDN7
PWDN7
/PWDN8
35
IOVDD PWDN8
IOVDD
34
MODE0
33
VCOM MODE1
32
VREFP FORMAT0
31
VREFN FORMAT1
30
FORMAT2
R4 49.9
29
AINP1 DRDY/FSYNC
AINN1
R6 49.9
28
SCLK
AINP2
27
AINN2 CLK
20 R7 49.9
AINP3 DOUT1
R8 49.9
19
AINN3 DOUT2
R9 49.9
18
DOUT3
R10 49.9
17
AINP4 DOUT4
R11 49.9
16
AINN4 DOUT5
R12 49.9
15
DOUT6
R13 49.9
14
AINP5 DOUT7
13 R14 49.9
AINN5 DOUT8
R15
12
AINP6 DIN
49.9
AINN6
R16 49.9
11
SYNC
AINP7
CONTROL.CLKDIV
10
AINN7 CLKDIV
R19
9
AINP8 TEST1
8
1.00k
AINN8 TEST0
6
AGND
GND
43
AGND
54
AGND
58
AGND
59
AGND
7
DGND
21
DGND
24
DGND
25
DGND
65
PowerPAD
ADS1278IPAPR
GND
VCOM
R5 49.9
2
1
J1
GND
CONTROL
CONTROL.CLKDIV
CLKDIV
CONTROL.MODE0
MODE0
CONTROL.MODE1
MODE1 CONTROL
CONTROL.FORMAT0
FORMAT0
CONTROL.FORMAT1
FORMAT1
CONTROL.FORMAT2
FORMAT2
IO
/DRDY_FSYNC
SCLK
DIN
/SYNC
CLK
DATA
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5 DATA
DOUT6
DOUT7
DOUT8
SBAU436 – JANUARY 2024
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