Texas Instruments ADS1278V2EVM-PDK User Manual page 20

Hardware Design Files
4 Hardware Design Files
This section contains the ADS1278 EVM schematics, and PCB layout, and bill of materials (BOM)
4.1 Schematics
This section shows the schematics for the ADS1278 EVM.
U2C
AVDD U2A
OPA2320AQDGKRQ1 OPA2320AQDGKRQ1
8 4
V+ V-
2
A
C8
VCOM_ADC
3
25V
0.1 µF GND
C9
25V
GND 0.1 µF
GND
VREFext
AVDD 2
1
J2
U3A GND
R22
R23
2 6
VIN VOUT
5
0
TRIM/NR
C12
1uF C15 C13
3 4
TEMP GND
1uF 10V
REF5025AIDGKT 10µF
GND
U3B
7
NC
1
DNC
8
DNC
REF5025AIDGKT
20 ADS1278EVM-PDK Evaluation Module
AVDD AVDD_ADC
R1
0
C2 C3 C4 C5 C1
25V 25V 25V 25V 10V
DVDD
R2
0.1 µF 0.1 µF 0.1 µF 0.1 µF 10µF
0
GND
VCOM
IOVDD IOVDD_ADC
R3
VCOM
0
1 R5 49.9 2
C7
1
10V
J1 10µF
GND
GND
VREFP
R18
R17 2.00k
0
VREFN
C11 150nF
R20
0
OPA2320AQDGKRQ1
U2B GND
6
R21 47.0
7
B
1.00k
5
C14
C16 25V
100 µF 0.1 µF
Figure 4-1. ADS1278 Connections Schematic
Copyright © 2024 Texas Instruments Incorporated
U1
5
AVDD PWDN1
44
AVDD PWDN2
53
AVDD PWDN3
60
AVDD PWDN4
DVDD_ADC
PWDN5
26
DVDD PWDN6
PWDN7
C6
22
IOVDD PWDN8
10V
23
IOVDD
10µF
MODE0
VCOM_ADC
55
VCOM MODE1
GND
VREFP 56
VREFP FORMAT0
VREFN 57
VREFN FORMAT1
FORMAT2
3
CHAN_P1 AINP1 DRDY/FSYNC
4
CHAN_N1
AINN1
SCLK
1
CHAN_P2 AINP2
2
CHAN_N2 AINN2 CLK
63
CHAN_P3 AINP3 DOUT1
64
CHAN_N3 AINN3 DOUT2
DOUT3
61
CHAN_P4
AINP4 DOUT4
62
CHAN_N4 AINN4 DOUT5
DOUT6
51
CHAN_P5 AINP5 DOUT7
52
CHAN_N5
AINN5 DOUT8
49
CHAN_P6 AINP6 DIN
50
CHAN_N6 AINN6
SYNC
47
CHAN_P7
AINP7
VREFP
48
CHAN_N7 AINN7 CLKDIV
45
CHAN_P8 AINP8 TEST1
C10
46
CHAN_N8
AINN8 TEST0
10V
10µF
AGND
VREFN
AGND
AGND
AGND
AGND
DGND
DGND
DGND
DGND
PowerPAD
ADS1278IPAPR
AVDD
/THSPD
IOVDD_ADC
J3
R24 100k
1 2
/PWDN1 R25 100k
3 4
5 6 /PWDN2 R26 100k
7 8 /PWDN3 R28 100k
/PWDN4 R30 100k
9 10
/PWDN5 R32 100k
11 12
13 14 /PWDN6 R34 100k
15 16 /PWDN7 R36 100k
/PWDN8 R38 100k
17 18
TSW-109-07-G-D
GND
42 /PWDN1
/PWDN2
41
/PWDN3
40
/PWDN4
39
38 /PWDN5
37 /PWDN6
/PWDN7 CONTROL
36
/PWDN8 CONTROL.CLKDIV
35
CLKDIV
34 CONTROL.MODE0
MODE0
CONTROL.MODE1
33
MODE1
32 CONTROL.FORMAT0
FORMAT0
31 CONTROL.FORMAT1
FORMAT1
CONTROL.FORMAT2
30
FORMAT2
29 R4 49.9
R6 49.9
28
27
CLK
DATA
R7 49.9
20
DOUT1
R8 49.9
19
DOUT2
R9 49.9
18
DOUT3
17 R10 49.9
DOUT4
R11 49.9
16
DOUT5 DATA
R12 49.9
15
DOUT6
R13 49.9
14
DOUT7
13 R14 49.9
DOUT8
R15
12
49.9
11 R16 49.9
CONTROL.CLKDIV
10
R19
9
8
1.00k
6
43 GND
54
58
59
7
21
24
25
65
GND
IOVDD_ADC
J4
1 2 CONTROL.MODE0 R27 100k
3 4 CONTROL.MODE1 R29 100k
CONTROL.FORMAT0 R31 100k
5 6
CONTROL.FORMAT1 R33 100k
7 8
9 10 CONTROL.FORMAT2 R35 100k
11 12 CONTROL.CLKDIV R37 100k
TSW-106-07-G-D
GND
SBAU436 – JANUARY 2024
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CONTROL
IO
/DRDY_FSYNC
SCLK
DIN IO
/SYNC