Texas Instruments ADS1278V2EVM-PDK User Manual page 21

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J6
IO./DRDY_FSYNC 1 2
CLK
3 4
DATA.DOUT2
5 6
DATA.DOUT4 7 8
DATA.DOUT6
9 10
DATA.DOUT8
11 12
IO./SYNC 13 14
15 16
TSW-108-07-G-D
GND
J7
1
IOVDD
GND
Y1
R42
4 3
VCC OUT
100k
C23
OSC ENABLE
25V
JP1 1 2
0.1 µF
ST GND
3
2
SG-210STF27.0000ML0
1
GND
Alternate: LMK6CA027000CDLFR
TSM-103-01-L-SV
OSC DISABLE
GND
SBAU436 – JANUARY 2024
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IO.SCLK
DATA.DOUT1
DATA.DOUT3
DATA.DOUT5
DATA.DOUT7
IO.DIN
EEPROM_WP
EVM CLK
JP2
3
MCLK_IN 2 R41
1
PHI_CLK TSM-103-01-L-SV
PHI CLK
GND
Figure 4-2. ADS1278 EVM Digital Connections Schematic
Copyright © 2024 Texas Instruments Incorporated
CONTROL
MODE0
MODE1
CONTROL FORMAT0
FORMAT1
FORMAT2
CLKDIV
IO.DIN
DIN
IO./DRDY_FSYNC
/DRDY_FSYNC
IO.SCLK
SCLK
CAP_CLK
IO MCLK_IN
IO
MCLK_OUT
DATA.DOUT1
IO./SYNC
/SYNC
PHI_CLK
IO
49.9 CLK
CLK
Hardware Design Files
J5
2 1
2 1
4 3
4 3
6 5
6 5
DATA.DOUT1
8 7
8 7 DOUT1
DATA.DOUT2
10 9
10 9 DOUT2
12 11 DATA.DOUT3
DOUT3
12 11
DATA.DOUT4
14 13
14 13 DOUT4
DATA.DOUT5
16 15
16 15 DOUT5
18 17 DATA.DOUT6
18 17 DOUT6
DATA.DOUT7
20 19
20 19 DOUT7
22 21 DATA.DOUT8
22 21 DOUT8
24 23
24 23
DATA
26 25
26 25
28 27
28 27
30 29
30 29
32 31
32 31
34 33
34 33
36 35
36 35
38 37
38 37
40 39
40 39
42 41
42 41
44 43
44 43
46 45
46 45
48 47
48 47
50 49 EEPROM_WP
50 49
52 51
52 51
54 53
54 53
EVM_ID_SDA 56 55 ID_PWR
56 55
EVM_ID_SCL
58 57
58 57
60 59
60 59
MP1 MP3
GND GND
MP2 MP4
GND GND
QTH-030-01-L-D-A
GND GND
ID_PWR
C22 R43
25V 10.0k
0.1 µF
U8
1 8
A0 VCC
GND
EEPROM_WP
2 7
A1 WP
3 6 EVM_ID_SCL
A2 SCL
EVM_ID_SDA
4 5
VSS SDA
C24
BR24G32FVT-3AGE2 25V
0.1 µF
GND GND
ADS1278EVM-PDK Evaluation Module
GND
DATA
DATA
MCLKo
MCLK_OUT
CAPCLK
CAP_CLK
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