Supermicro Super FatTwin F627G3-FT+ User Manual page 122

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FatTwin

F627G3-FT+/FTPT+/F73+/F73PT+ USER'S MANUAL

Intel

I/OAT

Select Enabled to enable Intel I/OAT (I/O Acceleration Technology), which

signiﬁ cantly reduces CPU overhead by leveraging CPU architectural demands,

freeing up the system resource for other tasks. The options are Disabled and

Enabled.

DCA Support

Select Enabled to use Intel's DCA (Direct Cache Access) Technology to improve

data transfer efﬁ ciency. The default setting is Enabled.

MMCFG BASE

This feature determines the lowest base address that can be assigned to PCI

devices. The lower the address, the less system memory is available (for 32-bit

OS). The higher the address, the less resources are allocated to PCI devices.

The options are 0x80000000, 0xA0000000, and 0xC0000000.

IIO 1 PCIe Port Bifurcation Control

This submenu conﬁ gures the following IO PCIe Port Bifurcation Control settings

for the PCIe ports. It also determines how the available PCI-Express lanes are

distributed between the PCI-Exp. Root ports.

CPU 1 Slot J1 PCI-E 3.0 x16 Link Speed

Select GEN1 to enable PCI-Exp Generation 1 support for Slot J1. Select GEN2

to enable PCI-Exp Generation 2 support for Slot J1. Select GEN3 to enable PCI-

Exp Generation 3 support for Slot J1. The options are GEN1, GEN2, and GEN3.

CPU 1 Slot J2 PCI-E 3.0 x8 Link Speed

Select GEN1 to enable PCI-Exp Generation 1 support for Slot J2. Select GEN2

to enable PCI-Exp Generation 2 support for Slot J2. Select GEN3 to enable PCI-

Exp Generation 3 support for Slot J2. The options are GEN1, GEN2, and GEN3.

CPU 1 Slot J3 PCI-E 3.0 x8 Link Speed

Select GEN1 to enable PCI-Exp Generation 1 support for Slot J3. Select GEN2

to enable PCI-Exp Generation 2 support for Slot J3. Select GEN3 to enable PCI-

Exp Generation 3 support for Slot J3. The options are GEN1, GEN2, and GEN3.

IIO 2 PCIe Port Bifurcation Control

This submenu conﬁ gures the following IO PCIe Port Bifurcation Control settings

for the PCIe ports. It also determines how the available PCI-Express lanes are

distributed between the PCI-Exp. Root Ports.

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