ADLINK Technology COM-HPC-sIDH User Manual page 41

COM-HPC-sIDH User's Guide
USB7+ A15
USB7- A14
USB0_SSTX0+ D44
USB0_SSTX0- D43
USB1_SSTX0+ D38
USB1_SSTX0- D37
USB0_SSTX1+ D47
USB0_SSTX1- D46
USB1_SSTX1+ D41
USB1_SSTX1- D40
USB0_SSRX0+ C45
USB0_SSRX0- C44
USB1_SSRX0+ C39
USB1_SSRX0- C38
USB0_SSRX1+ C48
USB0_SSRX1- C47
USB1_SSRX1+ C42
USB1_SSRX1- C41
USB2_SSTX+ D35
USB2_SSTX- D34
USB3_SSTX+ D32
USB3_SSTX- D31
USB2_SSRX+ C36
USB2_SSRX- C35
USB3_SSRX+ C33
USB3_SSRX- C32
Page 41
If any SuperSpeed ports are implemented, then they
must be supported by a USB 2.0 port, using one of
the USB[0:3] ports from this pool.
Four sets of SuperSpeed transmit pairs, used to
realize the transmit side of two USB 3.2 Gen 2x2
ports.
Alternatively, USB 3.2 Gen 1 or Gen 2 ports (single TX
pair, single RX pair per port) may be implemented
using a portion of this interface.
These ports shall be used in conjunction with the
corresponding USB 2.0 port pair (e.g. USB0_SSxxx+/-
shall be used with the USB0 USB 2.0 pair and so on,
USB1_SSxxx+/- with the USB1 USB 2.0 pair).
Four sets of SuperSpeed receive pairs, used to realize
the transmit side of two USB 3.2 Gen 2x2 ports.
Alternatively, USB 3.2 Gen 1 or Gen 2 ports (single TX
pair, single RX pair per port) may be implemented
using a portion of this interface.
These ports shall be used in conjunction with the
corresponding USB 2.0 port pair (e.g. USB0_SSxxx+/-
shall be used with the USB0 USB 2.0 pair and so on,
USB1_SSxxx+/- with the USB1 USB 2.0 pair).
Two sets of high speed transmit pairs, to realize two
USB 3.2 Gen 1 or Gen 2 implementations.
These ports shall be used in conjunction with the
corresponding USB 2.0 port pair (e.g. USB2_SSxxx+/-
shall be used with the USB2 USB 2.0 pair and
USB3_SSxxx+/- with the USB3 USB 2.0 pair).
Two sets of high speed receive pairs, to realize two
USB 3.2 Gen 1 or Gen 2 implementations.
These ports shall be used in conjunction with the
corresponding USB 2.0 port pair (e.g. USB2_SSxxx+/-
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O PCIe AC coupled on Module
I PCIe AC coupled off Module
O PCIe AC coupled on Module
I PCIe AC coupled off Module
PICMG COM-HPC R1.1