Chipset Overview - Supermicro X6DLP-EG2 User Manual

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Chipset Overview

The E7520 Chipset
Built upon the functionality and the capability of the 7520 chipset, the X6DLP-4G2/
X6DLP-EG2 motherboard provides the performance and feature set required for
dual processor-based servers, with confi guration options optimized for communica-
tions, presentation, storage, computation or database applications. The Intel E7520
chipset consists of the following components: the E7520 Memory Controller Hub
(MCH) and the 6300ESB I/O Controller Hub (6300ESB ICH).
The E7520 MCH supports Intel single or dual processors with Front Side Bus speeds
of up to 800 MHz; however, the Sossaman Processor supports FSB speeds of up
to 667 MHz. Its memory controller provides direct connection to two channels of
registered DDR2 with a marched system bus address and data bandwidths of up
to 5.4GB/s. The E7520 also supports the new PCI Express high speed serial I/O
interface for superior I/O bandwidth. The MCH provides three confi gurable x8 PCI
Express interfaces. These interfaces support connection of the MCH to a variety
of other bridges that are compliant with the PCI Express Interface Specifi cation,
Rev. 1.0a.
System Features
6300ESB
The I/O Controller Hub provides the I/O subsystem with access to the rest of the
system. It supports 2-channel Ultra ATA/100 Bus Master IDE Controller, two Serial
ATA (SATA) Host Controllers, SMBus 2.0 Controller, LPC/Flash BIOS Interface, PCI
2.3 Interface, and Integrated System Management Controller.
ICH System Features
6300ESB
The 6300ESB ICH system consists of an I/O Controller Hub, which provides the
I/O subsystem with an access to the rest of the system. Additionally, it integrates
many I/O functions.
Chapter 1: Introduction
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