Header Information - Texas Instruments TPSF12C1EVM-FILTER User Manual

www.ti.com
Meanwhile, Figure 2-4 shows a schematic that is designed for low-voltage testing of the active filter design,
including insertion loss measurement and EMI performance characterization. This facilitates an easy and
convenient verification of the active filter circuit prior to connection to a high-voltage switching regulator. A good
signal source and coupling capacitor provide CM excitation that mimics the CM noise source voltage and noise
source impedance related to the switch-node behavior of an actual power stage.
L
Dual
C
X1
LISN
2.2 F
N
GND
C
Y1
LISNs bonded 2.2 nF 2.2 nF
to the Ground
Reference
Plane for EMI
measurement
Chassis (PE)

2.3 Header Information

Table 2-1, Table 2-2 and Table 2-3
designated J2, J3 and J4 on the PCB facilitate oscillator signal injection and frequency sweep for measurement
of filter insertion loss or attenuation.
Header J1 specifically provides connections to the low-voltage side of the sense capacitors (corresponding to
the SENSE pins of the TPSF12C1), the low-voltage side of the inject capacitor, the IC bias power supply (VDD
and GND pins), which is set between 8 V and 16 V, and a remote enable (EN) signal.
(1)
POSITION LABEL
1 EN Enable input – leave open or tie high to enable the IC; tie to GND to disable
2 VDD Supply voltage connection – connect to a 12-V bias power supply referenced to GND
3 INJ Low-voltage terminal of the Y-rated inject capacitor, C10. Also connects to the AEF damping network
4 GND Ground – connect to the chassis ground of the system with a direct, low-inductance connection
5 S1 Low-voltage terminal of sense capacitor, C9. Also connects to the SENSE1A and SENSE1B pins of the IC
6 S2 Low-voltage terminal of sense capacitor, C8. Also connects to the SENSE2A and SENSE2B pins of the IC
(1) Pin positions of header J1 are designated right to left when viewed from the top side of the EVM.
(2) Working at an ESD-protected workstation, verify that any wrist straps, bootstraps or mats are connected and referencing the user to
earth ground before power is applied to the EVM.
SLVUCQ2A – JULY 2023 – REVISED JULY 2023
Submit Document Feedback
Filter board EVM with AEF
L
CM1
C
2.2 mH
2.2 F
C C C
C
SEN2 SEN1 INJ
Y2
680 pF 4.7 nF
680 pF
Chassis
(PE)
S2 S1 INJ VDD
J1
C
U1
VDD
NC IGND
TPSF12C1
VDD INJ
NC NC
SENSE1A COMP2
C
G2
SENSE1B
COMP1
SENSE2A REFGND
SENSE2B
EN
Figure 2-4. EVM Setup Schematic for Low-Voltage Testing
detail the various signal headers installed on the EVM. In addition, SMB jacks
Table 2-1. J1 Header Connections
Copyright © 2023 Texas Instruments Incorporated
L
CM2
C
2.2 mH
X2 X3
2.2 F
C
Y3
2.2 nF
Chassis (PE)
To enable the IC, leave EN open
EN
C
D3 R
D3
C
D1
R
D1A
R
D1
D
1
C
D2
C
G1
R
D2
R
G
DESCRIPTION
Active EMI Filter Evaluation Module for Single-Phase AC Power Systems
Hardware
L'
N'
C
SRC
1 nF
C
Y4
2.2 nF
Square-wave
CM excitation source
5 V pk-pk, 100 kHz
22% duty cycle
Chassis-referred VDD bias power = 12 V
= Dual LISN for EMI measurement
= Single-phase AEF IC
= Y-rated sense and inject capacitors
= 6-pin header
(2)
7