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3.4 Header Information
The EVM provides access to the DAC81401 digital pins through header J12.
definitions.
Pin Number
1
3
5
7
9
2,4,6,8,10
The pins on J12 can be used to externally control the DAC81401 with SPI commands if the FTDI controller is
disconnected from the DAC, by opening the J22 jumper.
3.5 Test Points
The DAC81401EVM has a variety of test points available for measuring and debugging purposes.
explains the purpose of each test point.
Test Point
TP4
TP6
TP7
TP8
TP9
TP10
TP12,TP13,TP14,TP16,TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
SLAU905 – AUGUST 2023
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Table 3-3. DAC81401EVM Header J12 Pin Definitions
Signal
FAULT
SYNC
SDO
SDI
SCLK
GND
Table 3-4. DAC81401EVM Test Points
Net
Description
DAC_VOUT
DAC81401 output
VREF
DAC81401 reference voltage
DAC8140 1 AVDD
AVDD
DAC81401 AVSS
AVSS
DAC81401 DVDD
DVDD
IOVDD
DAC81401 IOVDD
Ground connection
GND
Current flag output of OPA593 (U2)
Current flag (U2)
Thermal flag output of OPA593 (U2)
Thermal flag (U2)
DAC_OUT
High voltage gain BY 4× output for DAC81401 DAC_OUT
= 4×
Attenuated by 4X output for DAC81401 VSENSEP
DAC VSENSEP HV
3P3V
3.3-V LDO output
1P8V
1.8-V LDO output
TRIG
FTDI trigger pin
Copyright © 2023 Texas Instruments Incorporated
Table 3-3
Description
DAC81401 FAULT output
DAC81401 chip-select input
DAC81401 serial data output
DAC81401 serial data input
Serial-clock input
Ground
Hardware
lists the J12 pin
Table 3-4
DAC81401 Evaluation Module
13
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