Texas Instruments PCI7420 Manuals

Manuals and User Guides for Texas Instruments PCI7420. We have 1 Texas Instruments PCI7420 manual available for free PDF download: Implementation Manual

Texas Instruments PCI7420 Implementation Manual (81 pages)

Brand: Texas Instruments | Category: Computer Hardware | Size: 0 MB

Table of Contents
2
PCIXX20 Implementation Configuration
6
PCI7620 Implementation Configuration
6
PCI7420 Implementation Configuration
6
Figure 1. PCI7620 Typical System Implementation
6
PCI6620 Implementation Configuration
7
Figure 2. PCI7420 Typical System Implementation
7
Figure 3. PCI6620 Typical System Implementation
7
PCI6420 Implementation Configuration
8
Document Sections by Interfaces
8
Figure 4. PCI6420 Typical System Implementation
8
Power Considerations
9
Power Pin Description and Internal Voltage Regulator
9
Device Power Sequence
9
Bypass Capacitors
9
VCC
9
Ccb
9
Power Terminal Description
9
Vr_Port
10
VDPLL and Avdx
10
Flash Media Socket Power
10
Table 3
10
Requirements for Internal/External 1.8-V Core Power Supply
10
Power Switch Implementation
11
Cardbus Power Switch
11
Typical Power Switch Configuration
11
Figure 5. Power Switch Implementation
11
Flash Media Power Switch
12
PCI Bus Interface
13
PC Card Interface
15
Operation Modes
15
Implementing the PCIXX20 Controller as Single Cardbus Socket Device
15
Ultramedia™ Smart Card Interfaces
16
Table 7
16
Card Detect and Voltage Sense Connection for Ultramedia
16
Query Terminals - Voltage
16
Query Terminals - Smart Card Interface Implementation
16
Socket
17
Smart Card Terminals
17
CLK, RST, and I/O
18
General Layout Recommendations
18
Flash Media Interfaces
20
Dedicated Flash Media Socket
20
Universal Power Switch Implementation
20
Figure 6. Universal Flash Media Power Switch Implementation
20
Figure 7. Universal Flash Media Power Switch Implementation (SD/MMC Option)
21
Figure 8. Universal Flash Media Power Switch Implementation (MS/MSPRO Option)
21
Dedicated Secure Digital/Multimedia Card Socket
22
Figure 9. Universal Flash Media Power Switch Implementation (2-In-1 Option)
22
SD/MMC Terminals
23
Figure 10. SD/MMC Socket Connector Implementation
23
Dedicated Memory Stick/Memory Stick-Pro Card Socket
24
Figure 11. SD/MMC Power Switch Implementation
24
Figure 12. SD/MMC FET Power Switch Implementation
24
Table 10. MS/MSPRO Terminals
25
Figure 13. MS/MSPRO Socket Connector Implementation
25
Flash Media Support with 2-In-1 Socket Connector
26
Figure 14. MS/MSPRO Power Switch Implementation
26
Figure 15. MS/MSPRO FET Power Switch Implementation
26
Figure 16. 2-In-1 Socket Connector Implementation
27
Figure 17. 2-In-1 Power Switch Implementation
27
Figure 18. 2-In-1 FET Power Switch Implementation
28
PHY Port Cable Connection
29
Figure 19. TP Cable Connections
29
Figure 20. Typical Compliant DC Isolated Outer Shield Termination
29
Crystal Selection
30
Figure 21. Non-DC Isolated Outer Shield Termination
30
Figure 22. Load Capacitance for the PCI7X20 PHY
31
Figure 23. Recommended Crystal and Capacitor Layout
31
EMI Guidelines
32
Figure 24. Suggested Array at VDPLL and Avdx in Order to Minimize EMI
32
Disabling IEEE1394 Ports
33
Pin Strapping of the Unused 1394 Terminals
33
Table 11. Pin Strapping of the Unused 1394 Terminals
33
Miscellaneous Pin Interface
34
Multifunction Terminals
34
Spkrout
34
Suspend
34
Interrupt Configurations
35
Parallel PCI Interrupts Only
35
Serial IRQ and Parallel PCI Interrupts
35
Table 12. Interrupt Pin Register Cross Reference
35
Serial IRQ and Serial PCI Interrupts
36
Software Considerations
37
Cardbus and Ultramedia TM
37
EEPROM Configuration
37
Figure 25. EEPROM Implementation
37
Table 13. PCIXX20 EEPROM Loading Map
38
EEPROM Programming Guide
40
Serial ROM Offset 00H - Cardbus Function Indicator
40
Serial ROM Offset 01H - Number of Bytes in EEPROM Map
40
Serial ROM Offset 02H - Command Register (Function 0)
40
Serial ROM Offset 03H - Command Register (Function 1)
41
Serial ROM Offset 04H - Subsystem Vendor ID (Byte 0)
41
Serial ROM Offset 05H - Subsystem Vendor ID (Byte 1)
41
Serial ROM Offset 06H - Subsystem ID (Byte 0)
42
Serial ROM Offset 07H - Subsystem ID (Byte 1)
42
Serial ROM Offset 08H - PC Card Legacy-Mode Base Address Register (Byte 0)
42
Serial ROM Offset 09H - PC Card Legacy-Mode Base Address Register (Byte 1)
42
Serial ROM Offset 0Ah - PC Card Legacy-Mode Base Address Register (Byte 2)
42
Serial ROM Offset 0Bh - PC Card Legacy-Mode Base Address Register (Byte 3)
43
Serial ROM Offset 0Ch - System Control Register Byte 0 (Function 0)
43
Serial ROM Offset 0Dh - System Control Register Byte 0 (Function 1)
44
Serial ROM Offset 0Eh - System Control Register Byte 1
45
Serial ROM Offset 0Fh - System Control Register Byte 2
45
Serial ROM Offset 10H - System Control Register Byte 3
46
Serial ROM Offset 11H - Multifunction Routing Register Byte 0
47
Serial ROM Offset 12H - Multifunction Routing Register Byte 1
47
Serial ROM Offset 13H - Multifunction Routing Register Byte 2
48
Serial ROM Offset 14H - Multifunction Routing Register Byte 3
48
Serial ROM Offset 15H - Retry Status Register
48
Serial ROM Offset 16H - Card Control Register
49
Serial ROM Offset 17H - Device Control Register
49
Serial ROM Offset 18H - Diagnostic Register
50
Serial ROM Offset 19H - Power Management Capabilities Register (Function 0)
50
Serial ROM Offset 1Ah - Power Management Capabilities Register (Function 1)
51
Serial ROM Offset 1Dh - Exca Identification and Revision Register
51
Serial ROM Offset 1Eh - General Control Register
52
Serial ROM Offset 1Fh - General Control Register
52
Serial ROM Offset 20H - General-Purpose Event Enable Register
53
Serial ROM Offset 21H - General-Purpose Output Register
53
Serial ROM Offset 22H - 1394 OHCI Function Indicator
54
Serial ROM Offset 23H - Number of Bytes in the 1394 EEPROM Map
54
Serial ROM Offset 24H - Minimum Grant and Maximum Latency Register
54
Serial ROM Offset 25H Subsystem Identification Register
55
Serial ROM Offset 26H Subsystem Identification Register
55
Serial ROM Offset 27H Subsystem Identification Register (Byte 0)
55
Serial ROM Offset 28H Subsystem Identification Register (Byte 1)
56
Register
56
Serial ROM Offset 2Ah Mini-ROM Offset in EEPROM Map
57
Serial ROM Offset 2Bh GUID High Register (Byte 0)
57
Serial ROM Offset 2Ch GUID High Register (Byte 1)
57
Serial ROM Offset 2Dh GUID High Register (Byte 2)
57
Serial ROM Offset 2Eh GUID High Register (Byte 3)
58
Serial ROM Offset 2Fh GUID Low Register (Byte 0)
58
Serial ROM Offset 30H GUID Low Register (Byte 1)
58
Serial ROM Offset 31H GUID Low Register (Byte 2)
58
Serial ROM Offset 32H GUID Low Register (Byte 3)
59
Serial ROM Offset 34H Link Enchancement Control Register
59
Serial ROM Offset 35H PCI Miscellaneous Configuration Register (Byte 0)
60
Serial ROM Offset 36H PCI Miscellaneous Configuration Register (Byte 1)
61
Serial ROM Offset 3Ah PCI PHY Layer Control Register
61
Serial ROM Offset 3Bh Flash Media Core Function Indicator
62
Serial ROM Offset 3Ch Number of Bytes in EEPROM Map (Flashmedia)
62
Serial ROM Offset 3Dh Subsystem Vendor Identification Register (Byte 0)
62
Serial ROM Offset 3Eh Subsystem Vendor Identification Register (Byte 1)
62
Serial ROM Offset 3Fh Subsystem Identification Register (Byte 0)
62
Serial ROM Offset 40H Subsystem Vendor Identification Register (Byte 1)
63
Serial ROM Offset 41H General Control Register (Function 3)
63
Serial ROM Offset 42H End-Of-List Indicator
63
Socket Power Lock
64
VCC Protection
64
BIOS Considerations
64
Power Management Considerations
65
D3 Wake Information
65
GRST -Only Registers
66
PME Context Registers
68
Table 14. Cardbus CSTSCHG and Wake-Up Signals Truth Table
69
Table 15. 16 Bit Card RI/STSCHG and Wake-Up Signals Truth Table
69
CLKRUN Protocol
70
Suspend
70
Migration to PCIXX20 from PCI7X10
71
Hardware and Pin Assignment Changes
71
Software Changes
71
Configuration Register Changes
72
Function 0 and Function 1 - Cardbus
72
Function 2 - 1394
74
Function 3 - Flash Media
74
Migration to PCIXX20 from PCI1620
75
Hardware and Pin Assignment Changes
75
Software Changes
75
Configuration Register Changes
76
Function 0 and Function 1 - Cardbus
76
Function 2 - 1394 (PCI7X20 Only)
78
Function 3 - Flash Media
78
Dedicated Smartcard Implementation Schematic
79
Reference Schematics
80
References
80

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