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PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide
This document is provided to assist platform designers using the PCIXX20 (PCI7620,
PCI7420, PCI6620, or PCI6420) dual-socket CardBus and SmartCard controller with
integrated 1394a and dedicated Secure Digital/Multimedia Card and Memory
Stick/Memory Stick-Pro sockets. Detailed information can be found in the PCIXX20 data
manual. However, this document provides design suggestions for the various options
when designing in the PCIXX20 controller.
This document covers implementation guidance for all four PCIXX20 controllers. In order
to efficiently utilize this document, each controller with its relevant sections is listed below:
ABSTRACT
HOW TO USE THIS DOCUMENT
Section
PCI7620
1
1.1
2
All
3
All
4
All
5
All
6
All
7
All
8
All
9
All
10
All
11
All
12
All
13
All
PCI7420
PCI6620
1.2
1.3
All
All
All
All
All
All
All
All
-
All
All
All
All
8.3
All
All
All
All
All
All
All
All
-
All
Application Report
SCPU019 - July 2003
Computer Connectivity Solutions
PCI6420
1.4
All
All
All
All
-
All
8.3
All
All
All
All
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1
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Table of Contents
Related Manuals for Texas Instruments PCI7620
Summary of Contents for Texas Instruments PCI7620
- Page 1 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide Computer Connectivity Solutions ABSTRACT This document is provided to assist platform designers using the PCIXX20 (PCI7620, PCI7420, PCI6620, or PCI6420) dual-socket CardBus and SmartCard controller with integrated 1394a and dedicated Secure Digital/Multimedia Card and Memory Stick/Memory Stick-Pro sockets. Detailed information can be found in the PCIXX20 data manual.
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Page 2: Table Of Contents
SCPU019 Contents PCIXX20 Implementation Configuration ..................6 1.1 PCI7620 Implementation Configuration .................. 6 1.2 PCI7420 Implementation Configuration .................. 6 1.3 PCI6620 Implementation Configuration .................. 7 1.4 PCI6420 Implementation Configuration .................. 8 Power Considerations ......................... 9 2.1 Power Pin Description and Internal Voltage Regulator ............9 2.2 Device Power Sequence ...................... - Page 3 Serial ROM Offset 2Fh - GUID Low Register (Byte 0) ........... 58 11.3.47 Serial ROM Offset 30h - GUID Low Register (Byte 1) ........... 58 11.3.48 Serial ROM Offset 31h - GUID Low Register (Byte2) ..........58 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide...
- Page 4 14.3.1 Function 0 and Function 1 - CardBus................ 76 14.3.2 Function 2 – 1394 (PCI7X20 Only) ................78 14.3.3 Function 3 – Flash Media..................78 Dedicated SmartCard Implementation Schematic ..............79 Reference Schematics ....................... 80 References..........................80 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide...
- Page 5 CardBus CSTSCHG and Wake-Up Signals Truth Table ..........69 Table 15. 16 Bit Card RI/STSCHG and Wake-Up Signals Truth Table ........69 Figures Figure 1. PCI7620 Typical System Implementation............... 6 Figure 2. PCI7420 Typical System Implementation............... 7 Figure 3. PCI6620 Typical System Implementation............... 7 Figure 4.
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Page 6: Pcixx20 Implementation Configuration
PCI6420 controller 1.1 PCI7620 Implementation Configuration The PCI7620 (device ID 0xAC8Dh) controller supports five functions (CardBus, Smart Card, Secure Digital/Multimedia Card, Memory Stick/Memory Stick-Pro, and IEEE 1394a), all of which can be individually enabled or disabled. For more product information, please refer to the PCI7620 data manual at http://www.ti.com. -
Page 7: Pci6620 Implementation Configuration
Please refer to Table 1 for interface-related sections. PCI BUS SD/MMC EEPROM Power Switch PCI6620 (Optional) MS/MSPRO Card Card Power Switch NCN 6000 NCN 6000 Smart Card Smart Card Figure 3. PCI6620 Typical System Implementation PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 8: Pci6420 Implementation Configuration
PCI BUS SD/MMC EEPROM Power Switch PCI6420 (Optional) MS/MSPRO Card Card Power Switch Figure 4. PCI6420 Typical System Implementation Table 1. Document Sections by Interfaces Interfaces Section Device Power Power Switch CardBus EEPROM Smart Card Flash Media 1394 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 9: Power Considerations
2.3 Bypass Capacitors Standard design rules for the power supply bypass must be followed. The following sections are bypass capacitors recommended by Texas Instruments. 2.3.1 V , and V A 0.1-µF bypass capacitor is recommended for each of these power terminals. -
Page 10: Vr_Port
0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. 2.3.4 Flash Media Socket Power A parallel combination of a 0.01-µF capacitor and a 10-µF capacitor placed on the power source close to the flash media socket is recommended. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 11: Power Switch Implementation
3.3VIN 3.3VIN TPS2228 (DB) 0.1uF 10uF Figure 5. Power Switch Implementation Table 4. Typical Power Switch Configuration Voltage Requirement Power Switch 12V_SW_SEL 1.8 V, 3.3 V, 5 V TPS2228 (recommended) 3.3 V, 5 V, 12 V TPS222x PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 12: Flash Media Power Switch
32 kHz and 100 kHz. If the internal clock is used, then a 43-k Ω pulldown resistor is necessary. 3.2 Flash Media Power Switch Details on Flash Media power switch implementation are described in Section 7. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 13: Pci Bus Interface
Refer to Section 2 of the PCI Mobile Design Guide Revision 1.1. This signal is required for ACPI systems. In a notebook PC, this signal is usually connected to the south bridge or embedded controller (EC). The PME terminal uses an open-drain type buffer. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... - Page 14 STOP , DEVSEL , PERR , SERR , LOCK , INTA , INTB , INTC , INTD , CLKRUN , and PME . GRST requires a pullup resistor if the controlling output does not drive high. Please refer to PCI Local Bus Specification , Revision 2.3 for precise values of pullup resistors. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide...
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Page 15: Pc Card Interface
B interface unconnected. The DISABLE_SKTB bit (general control register, PCI offset 86h, bit 4) must be set to disable function 1 (CardBus socket B). This bit can be set via EEPROM or BIOS. Unused CardBus socket terminals must be left floating (no connection). PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 16: Ultramedia™ Smart Card Interfaces
SCPU019 6 UltraMedia™ Smart Card Interfaces In order to configure one or both of the PCIX620 (PCI7620 or PCI6620) UltraMedia™ CardBus sockets to be a Smart Card (SC) compatible socket, an SC socket connector (AMP 145300-1 or equivalent) and an SC electrical interface (NCN6000 or equivalent) must be used. An SC socket connector mechanically supports and recognizes a PCIX620-supported Smart Card. -
Page 17: Socket
NCN6000 power switch. A 22-µH inductor (L2) with an ESR less than 2 Ω is recommended to optimize the dc/dc conversion efficiency. The Murata LQH3C220K04 or equivalent is suggested. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 18: Clk, Rst, And I/O
Placement of C20 on SC_VCC must be near the socket to prevent large transients on the socket during the switched load tests. The placement of components R17, R18, R19, C17, C18, and C19 are not as critical and can be placed near the NCN6000 power switch or the socket, whichever is convenient. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... - Page 19 NCN6000 power switch. If an option is included, then a 0- Ω resistor may be populated by default and populated with the ferrite only if it is found that the supply voltage input is excessively noisy. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide...
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Page 20: Flash Media Interfaces
Stick-Pro (MS/MSPRO). The two dedicated flash media sockets can be used concurrently. 7.1.1 Universal Power Switch Implementation Due to the cross-platform consideration for many system designers, Texas Instruments has implemented a power switch implementation that maximizes the configurability and minimizes routing and layout changes for the flash media implementation. -
Page 21: Figure 7. Universal Flash Media Power Switch Implementation (Sd/Mmc Option)
U1-NF-1 EVM3.3V MS/MSPRO_VCC SD/MMC_VCC MC_PWR_CTRL_1 0-NF SN74AUC1GU04 Single Input Inverter Gate 0 - NF U2-1 BSO 203SP 0 -NF MC_PWR_CTRL_0 SN74AUC1GU04 100K-NF 100K Single Input Inverter Gate Figure 8. Universal Flash Media Power Switch Implementation (MS/MSPRO Option) PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 22: Dedicated Secure Digital/Multimedia Card Socket
If system designers wish to employ a more optimized implementation, please see Sections 7.2.2.2 and 7.2.3.2. 7.1.2 Dedicated Secure Digital/Multimedia Card Socket In order to take advantage of the dedicated SD/MMC socket, a SD/MMC flash media socket connector and a 3.3-V power switch are recommended. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 23: Sd/Mmc Terminals
Place close to socket VCC_SD/MMC SD_SKT_DAT3 10uF .01uF SD_DAT3 DAT3 SD_SKT_CMD SD_CMD VSS1 SD_SKT_CLK SD_CLK VSS2 SD_SKT_DAT0 SD_DAT0 DAT0 SD_SKT_DAT1 SD_DAT1 DAT1 SD_SKT_DAT2 SD_DAT2 DAT2 SKT_MC_CD_0# MC_CD_0# COMMON SD_WP SD_WP SD_WP SD_CONNECTOR Figure 10. SD/MMC Socket Connector Implementation PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 24: Dedicated Memory Stick/Memory Stick-Pro Card Socket
Figure 12. SD/MMC FET Power Switch Implementation 7.1.3 Dedicated Memory Stick/Memory Stick-Pro Card Socket In order to take advantage of the dedicated MS/MSPRO socket, a MS/MSPRO flash media socket connector and a 3.3-V power switch are recommended. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 25: Table 10. Ms/Mspro Terminals
System designers can power the MS/MSPRO socket connector by using either a power switch (TPS2030 or equivalent) or a FET power switch implementation. If a power switch is chosen, then a 0.1-µF bypass capacitor connected between MS/MSPRO V and GND is recommended. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 26: Flash Media Support With 2-In-1 Socket Connector
Trace lengths on all SD/MMC and MS/MSPRO interface signals must be kept similar to each other to minimize the difference in propagation delay and capacitance. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 27: Figure 16. 2-In-1 Socket Connector Implementation
TPS2030 .1uF Single 2-Input Positive-OR Gate Figure 17. 2-In-1 Power Switch Implementation If the FET power switch implementation is desired, then a NOR gate (SN75AHCT1G02 or equivalent) and a P-channel transistor (BSO 203SP or equivalent) are recommended. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 28: Figure 18. 2-In-1 Fet Power Switch Implementation
SCPU019 EVM3.3V FLASHMEDIA_3.3V U1-1 MC_PWR_CTRL_0 MC_PWR_CTRL_1 P-Channel Transistor SN74AHCT1G02 100K Single 2-Input Positive-NOR Gate Figure 18. 2-In-1 FET Power Switch Implementation PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 29: Phy Port Cable Connection
NOTE A: IEEE Std 1394–1995 calls for a 250–pF capacitor, which is a nonstandard component value. A 220–pF capacitor is recommended. Outer Cable Shield 1 MΩ 0.01 µF 0.001 µF Chassis Ground Figure 20. Typical Compliant DC Isolated Outer Shield Termination PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 30: Crystal Selection
Figure 21. Non-DC Isolated Outer Shield Termination 8.1 Crystal Selection The PCI7X20 (PCI7620 or PCI7420) controller is designed to use an external 24.576-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates. -
Page 31: Figure 22. Load Capacitance For The Pci7X20 Phy
PHY X1 and X0 pins to minimize etch lengths, as shown in Figure 22. Figure 23. Recommended Crystal and Capacitor Layout For more details on crystal selection, see application report SLLA051 available from the TI website: http://www.ti.com/sc/1394. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 32: Emi Guidelines
Plane 0.001 0.01 10 µF µF 1 µF µF Figure 24. Suggested Array at VDPLL and AVDx in Order to Minimize EMI For additional electromagnetic interference (EMI) guidelines and recommendations send a request via e-mail to 1394-EMI@list.ti.com. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 33: Disabling Ieee1394 Ports
No connect TPA1N No connect TPBIAS0 No connect TPBIAS1 No connect TPB0P Pull directly to GND TPB0N Pull directly to GND TPB1P Pull directly to GND TPB1N Pull directly to GND Pull directly to GND No connect PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 34: Miscellaneous Pin Interface
Gating PCLK makes the IRQSER state machine stop until SUSPEND is deasserted. Two requirements for implementing the suspend mode are: o The PCI bus must not be parked on the PCIXX20 controller. o IRQSER signaling is not proceeding when SUSPEND is asserted. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 35: Interrupt Configurations
INTA can be routed through the PCI edge connector while IRQSER must be attached to a serial IRQ input on the motherboard. If no serial IRQ input is available, then this mode still allows CardBus cards to function properly. However, some 16-bit cards may not. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 36: Serial Irq And Serial Pci Interrupts
PCI add-in cards if an IRQSER input is available in the system. It is the simplest method of routing interrupts and allows the other multifunction terminals to be used for other purposes. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 37: Software Considerations
However, due to the added support for UltraMedia functions, new drivers and .inf files provided by Texas Instruments must be used. These drivers and .inf files allow the Flash Media function to be reported in device manager properly. To shorten system setup time, an install shield package for Windows 2000 and XP is provided by Texas Instruments to simplify the configuration process. -
Page 38: Table 13. Pcixx20 Eeprom Loading Map
ExCA 800h, ExCA identification and revision, bits 7-0 PCI 86h, general control, byte 0, bits 5, 4, 3, 1, 0 PCI 87h, general control, byte 1, bits 4-2 PCI 89h, GPE enable, bits 7, 6, 4-0 PCI 8Bh, general-purpose output, bits 4-0 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... - Page 39 Number of bytes (05h) PCI 2Ch, subsystem vendor ID, byte 0 PCI 2Dh, subsystem vendor ID, byte 1 PCI 2Eh, subsystem ID, byte 0 PCI 2Fh, subsystem ID, byte 1 PCI 4Ch, general control bits 6-0 End-of-list indicator (80h) PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide...
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Page 40: Eeprom Programming Guide
Memory space enable. This bit controls whether or not the PCIXX20 controller can claim cycles in MEM_EN PCI memory space. I/O space control. This bit controls whether or not the PCIXX20 controller can claim cycles in PCI IO_EN I/O space. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 41: Serial Rom Offset 03H - Command Register (Function 1)
Serial ROM offset 05h corresponds to byte 1 of the subsystem vendor ID register (PCI offset 41h). To ensure proper device driver functionality, this offset must be set as follows: Serial ROM Offset 05h Bit Number Recommended value PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 42: Serial Rom Offset 06H - Subsystem Id (Byte 0)
Serial ROM Offset 0Ah – PC Card Legacy-Mode Base Address Register (Byte 2) Serial ROM offset 0Ah corresponds to byte 2 of the PC Card legacy-mode base address register (PCI offset 46h). Serial ROM Offset 0Ah Bit Number Typical value PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 43: Serial Rom Offset 0Bh - Pc Card Legacy-Mode Base Address Register (Byte 3)
(RIENB) of the card control register is 0, then the output is placed in a high-impedance state. 0 = RI_OUT signal is routed to the PME / RI_OUT terminal if bit 7 of the card control register is 1. 1 = PME signal is routed to the PME / RI_OUT terminal. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 44: Serial Rom Offset 0Dh - System Control Register Byte 0 (Function 1)
(RIENB) of the card control register is 0, then the output is placed in a high-impedance state. 0 = RI_OUT signal is routed to the PME / RI_OUT terminal if bit 7 of the card control register is 1 = PME signal is routed to the PME / RI_OUT terminal. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 45: Serial Rom Offset 0Eh - System Control Register Byte 1
Serial ROM Offset 0Fh – System Control Register Byte 2 Serial ROM offset 0Fh corresponds to byte 2 of the system control register (PCI offset 82h). This offset is reserved and all 0s must be loaded. Serial ROM Offset 0Fh Bit Number Typical value PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 46: Serial Rom Offset 10H - System Control Register Byte 3
RSVD Reserved SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt SMIENB when a write to the socket power control occurs. This bit is shared between functions 0 and 1. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 47: Serial Rom Offset 11H - Multifunction Routing Register Byte 0
0001 = GPO2 0101 = IRQ5 1001 = IRQ9 1101 = TEST_MUX MFUNC2 0010 = PCREQ 0110 = RSVD 1010 = IRQ10 1110 = GPE 0011 = IRQ3 0111 = RSVD 1011 = INTC 1111 = IRQ7 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 48: Serial Rom Offset 13H - Multifunction Routing Register Byte 2
0 = PCI retry counter disabled 1 = PCI retry counter enabled CardBus retry time-out counter enable. This bit is encoded as: CBRETRY 0 = CardBus retry counter disabled 1 = CardBus retry counter enabled RSVD Reserved PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 49: Serial Rom Offset 16H - Card Control Register
Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded: 00 = Parallel PCI interrupts only INTMODE 01 = Reserved 10 = IRQ serialized interrupts and parallel PCI interrupts INTA , INTB , INTC , INTD 11 = IRQ and PCI serialized interrupts RSVD Reserved PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 50: Serial Rom Offset 18H - Diagnostic Register
PME_EN bit. This bit is cleared by a write back of 1, and this PMESTAT also clears the PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect. RSVD Reserved PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 51: Serial Rom Offset 1Ah - Power Management Capabilities Register (Function 1)
82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the PCIXX20 controller. Host software can read this field to determine compatibility to the 365REV 82365SL-DF register set. This field defaults to 0100b upon reset. Writing 0010b to this field places the controller in the 82356SL mode. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 52: Serial Rom Offset 1Eh - General Control Register
Power switch select. This bit selects which power switch is implemented in the system. 12V_SW_SEL 0 = A 1.8-V capable power switch (TPS2228) is used. 1 = A 12-V capable power switch (TPS2226) is used. RSVD Reserved PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 53: Serial Rom Offset 20H - General-Purpose Event Enable Register
This bit represents the logical value of the data driven to GPO2. GPO1_DATA This bit represents the logical value of the data driven to GPO1. GPO0_DATA This bit represents the logical value of the data driven to GPO0. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 54: Serial Rom Offset 22H - 1394 Ohci Function Indicator
PCI7X20 controller. The default for this register indicates that the PCI7X20 controller may MIN_GNT need to sustain burst transfers for nearly 64 µs and thus request a large value be programmed in bits 15-8 of the PCI7X20 latency timer and class cache line size register at PCI offset 0Ch. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 55: Serial Rom Offset 25H Subsystem Identification Register
PCI6X20 controller since the PCI6X20 controller does not have a 1394 function. Serial ROM Offset 27h Bit Number Recommended value Field Name Description OHCI_SSID Subsystem device ID. This field indicates the first byte of the subsystem device ID. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 56: Serial Rom Offset 28H Subsystem Identification Register (Byte 1)
RSVD Reserved Enable acceleration enhancements. OHCI-Lynx™ compatible. When this bit is set, the enab_accel PHY layer is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. RSVD Reserved PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 57: Serial Rom Offset 2Ah Mini-Rom Offset In Eeprom Map
Serial ROM offset 2Dh corresponds to byte 2 of the GUID high register (OHCI offset 24h). This serial ROM offset is RSVD for the PCI6X20 controller since the PCI6X20 controller does not have a 1394 function. Serial ROM Offset 2Dh Bit Number Typical value PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 58: Serial Rom Offset 2Eh Guid High Register (Byte 3)
Serial ROM offset 31h corresponds to byte 2 of the GUID low register (OHCI offset 28h). This serial ROM offset is RSVD for the PCI6X20 controller since the PCI6X20 controller does not have a 1394 function. Serial ROM Offset 31h Bit Number Typical value PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 59: Serial Rom Offset 32H Guid Low Register (Byte 3)
An AT threshold of 2K results in a store-and-forward operation, which means that asynchronous data is not transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results in only complete packets being transmitted. RSVD Reserved PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 60: Serial Rom Offset 35H Pci Miscellaneous Configuration Register (Byte 0)
The GPIO3 and GPIO2 terminals are also placed in the high-impedance state. RSVD Reserved When this bit is set, the PCI clock is always kept running through the CLKRUN protocol. KEEP_PCLK When this bit is cleared, the PCI clock can be stopped using CLKRUN on the MFUNC terminals. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 61: Serial Rom Offset 36H Pci Miscellaneous Configuration Register (Byte 1)
PCI6X20 controller does not have a 1394 function. Serial ROM Offset 3Ah Bit Number Typical value Field Name Description wrData This field is the data to be written to a PHY register and is ignored for reads. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 62: Serial Rom Offset 3Bh Flash Media Core Function Indicator
Serial ROM offset 3Fh corresponds to byte 0 of the subsystem identification register (PCI offset 2Eh) of function 3. To ensure proper device driver functionality, this offset must be set as follows: Serial ROM Offset 3Fh Bit Number Recommended value PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 63: Serial Rom Offset 40H Subsystem Vendor Identification Register (Byte 1)
Serial ROM Offset 42h End-of-List Indicator Serial ROM offset 42h corresponds to an end-of-list indicator denoting the end of EEPROM map. This offset has a recommended value of 80h. Serial ROM Offset 40h Bit Number Recommended value PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 64: Socket Power Lock
Other registers may need to be changed according to system implementation. The following sections contain explanations of registers which are frequently asked about. Microsoft provides the following reference documents concerning initialization of CardBus controllers in Windows: http://www.microsoft.com/hwdev/bus/cardbus/cardbus1.asp http://www.microsoft.com/hwdev/bus/pci/pcibridge-cardbus.asp PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 65: Power Management Considerations
Vaux to be supplied and the pullup resistor on PME must also be connected to Vaux. In addition, the V pins and power switch must also have power in order to wake from a card. Vaux is limited to 200 mA for the socket. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 66: Grst -Only Registers
Serial bus slave address register (PCI offset B2h) bits 7-0 o Serial bus control/status register (PCI offset B3h) bits 7, 3-0 o ExCA identification and revision register (ExCA offset 800h/840h) bits 7-0 o ExCA global control register (ExCA offset 81Eh/85Eh) bits 2-0 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... - Page 67 Subsystem ID register (PCI offset 2Eh): bits 15-0 o Power management control status register (PCI offset 48h): bits 15, 8, 1-0 o General control (PCI offset 4Ch): bits 6-5, 4, 2-0 o PLL control register (PCI offset 54h): bits 31-0 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide...
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Page 68: Pme Context Registers
PCIXX20 controller can also provide RI_OUT on the multifunction terminals. To enable passage of ring signals from the PC Card interface, RINGEN (bit 7 ExCA offset 803h) must be set to 1, and RIENB (bit 7 PCI offset 91h) must be set to 1. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 69: Table 14. Cardbus Cstschg And Wake-Up Signals Truth Table
Latched CSTSCHG CSTSCHG Table 15. 16 Bit Card RI/STSCHG and Wake-Up Signals Truth Table RINGEN RIMUX RIENB PME_EN PME_STAT MFUNC7 RI_OUT / PME Latched Latched Latched Latched RI Latched Latched Latched Latched Latched RI Latched Latched Latched RI PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 70: Clkrun Protocol
If a 3.3-V card is inserted into the hot slot that was powered to 5 V, then card damage may occur. It is therefore recommended that P2CCLK, bit 27 at PCI offset 80h, is set to 1 so that the internal oscillator is enabled. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 71: Migration To Pcixx20 From Pci7X10
PCI1620 controller, please refer to Section 11 for detailed EEPROM implementation. • INTD is now supported by the PCIXX20 controller. • PCI function 1 is changed to support CardBus socket A, and function 3 is changed to support the dedicated Flash Media sockets. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 72: Configuration Register Changes
Bits 9-8 are changed to RSVD bits. Read-only, return 0 when read. o Bit 7 is designated PCI2_3_EN bit. Read-only, default 1. o Bit 5 is changed to DISABLE_FM bit. Read-write, default 0. o Bit 4 is changed to DISABLE_SKTB bit. Read-write, default 0. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... - Page 73 Bit 11 is changed to RSVD bit. Read-only, returns 0 when read. o Bit 10 is changed to RSVD bit. Read-only, returns 1 when read. o Bit 9 is changed to RSVD bit. Read-only, returns 0 when read. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide...
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Page 74: Function 2 - 1394
A set of PCI configuration registers in function 3 of the PCIXX20 controller is significantly different from that of the PCI7X10 controller. Please refer to the PCIXX20 data manual which can be located at the IT web portal at http://www.ti.com. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 75: Migration To Pcixx20 From Pci1620
EEPROM loading map of the PCIXX20 controller is significantly different than that of the PCI1620 controller, please refer to Section 11 for detailed EEPROM implementation. • PCI function 2 now supports 1394 for PCI7X20 controller, and function 3 is added to support the dedicated Flash Media sockets. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 76: Configuration Register Changes
Bit 13 is designated SIM_MODE bit. Read-write, default 0. o Bit 12 is designated IO_LIMIT_SEL bit. Read-write, default 0. o Bit 11 is designated IO_BASE_SEL bit. Read-write, default 0. o Bit 10 is designated 12V_SW_SEL bit. Read-write, default 0. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... - Page 77 0111 is changed to RSVD o Bits 3-0 values: 0110 is changed to RSVD 0111 is changed to RSVD • Card control register (PCI offset 91h) o Bits 6-5 are changed to RSVD bits. Read-only, returns 0 when read. PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide...
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Page 78: Function 2 - 1394 (Pci7X20 Only)
A set of PCI configuration registers are added to function 3 of the PCIXX20 controller. Please refer to the PCIXX20 data manual which can be located at the IT web portal at http://www.ti.com. • Interrupt pin register (PCI offset 3Dh) o Default value is changed to 04h PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 79: Dedicated Smartcard Implementation Schematic
CRD_CLK CRD_CLK SC_GPIO6 SC_GPIO6 CRD_RST CRD_RST SC_CLK SC_CLK RC_CD# CLOCK_IN CRD_DET 4.7 uF NCN6000D 10 uF 0.01 uF SC_VCC CRD_RST CARD_IO CRD_CLK CRD_IO SC_CD# Smart Card Connector 100 pF_NF 22K_NF 145300-1 56 pF 470 pF 0.1 uF PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide... -
Page 80: Reference Schematics
16 Reference Schematics Please refer to the PCIXX20 EVM schematics for use as reference schematics. 17 References 1. PCI7620/PCI7420 Dual Socket CardBus and SmartCard Controller With Integrated 1394 and Dedicated SD/MS-PRO Sockets Data Manual from the Texas Instruments Web portal at http://www.ti.com 2. - Page 81 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
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