UM2407
6.7
Solder bridges and jumpers
SBxx can be found on the top layer and SB1xx can be found on the bottom layer of the
Nucleo-144 board.
Bridge
SB1 (3V3_PER)
SB2 (3V3)
SB80 (1V8_VDD)
SB12, SB19 (ST-LINK-
USART)
JP1 (ST-LINK_RST)
(SWO)
(NRST)
SB10, SB11, SB20
(IOREF)
Table 14. Solder bridge and jumper configuration
State
ON
OFF
ON
OFF
ON
OFF
ON
SB6
OFF
ON
OFF
OFF
ON
ON
SB32
OFF
ON
JP3
OFF
OFF, ON,
OFF
ON, OFF,
OFF
OFF, OFF,
ON
(1)
Peripheral power 3V3_PER is connected to 3V3.
Peripheral power 3V3_PER is not connected.
Output of voltage regulator ST1L05CPU33R is connected to
3V3.
Output of voltage regulator ST1L05CPU33R is not
connected.
Output of voltage regulator ST1L05BPUR is connected to
1V8_VDD.
Output of voltage regulator ST1L05BPUR is not connected.
Input of voltage regulator ST1L05BPUR is connected to
3V3_VDD.
Input of voltage regulator ST1L05BPUR is not connected.
PG9 and PG14 on ST-LINK STM32F723IEK6 are connected
to PD8 and PD9 to enable the Virtual COM port. Thus, PD8
and PD9 on the ST morpho connectors cannot be used.
PG9 and PG14 on ST-LINK STM32F723IEK6 are
disconnected from PD8 and PD9 on STM32H7.
No incidence on ST-LINK STM32F723IEK6 NRST signal.
ST-LINK STM32F723IEK6 signal is connected to GND
(ST-LINK reset to reduce power consumption).
SWO signal of the STM32H7 (PB3) is connected to the ST-
LINK SWO input.
(SB26 must be OFF)
SWO signal of STM32H7 is not connected.
Board RESET signal (NRST) is connected to ST-LINK reset
control I/O (T_NRST).
Board RESET signal (NRST) is not connected to ST-LINK
reset control I/O (T_NRST).
IOREF is connected to VDD_MCU.
IOREF is connected to 3V3_PER.
IOREF is connected to 3V3.
UM2407 Rev 3
Hardware layout and configuration
Description
29/49
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