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■ When [Exposure Mode] is [Off]
• Line Start Trigger Off
EEN
LVAL
DVAL
• Common to [Binning Off] and [Vertical Binning On]
TapGeometry
Bit/Pixel
1X2
8/10
1X3
8
1X4
8/10
1X8
8/10
1X10
8
*) About CL Pixel Clock [MHz] and time of 1Clock
CL Pixel Clock [MHz] : 31.70
CL Pixel Clock [MHz] : 42.41
CL Pixel Clock [MHz] : 63.39
CL Pixel Clock [MHz] : 84.82
A
//
B
//
//
CL Pixel
Line Period
Clock[MHz]
(CLK) [A]
31.70
2058
42.41
2065
63.39
2058
84.82
2066
31.70
1371
42.41
1376
63.39
1372
84.82
1376
31.70
1029
42.41
1033
63.39
1030
84.82
1034
31.70
515
42.41
517
63.39
516
84.82
518
31.70
412
42.41
413
63.39
412
84.82
425
1CLK : 0.0315μs
1CLK : 0.0236μs
1CLK : 0.0158μs
1CLK : 0.0118μs
— 23 —
C
D
E
Actual
EEN invalid
Exposure
time (μs) [C]
Time (μs) [B]
61.32
3.6
45.09
3.6
28.87
3.6
20.76
3.6
39.65
3.6
28.85
3.6
18.04
3.6
12.62
3.6
28.86
3.6
20.76
3.6
12.65
3.6
8.59
3.6
12.65
3.6
8.59
3.6
4.54
3.6
2.51
3.6
9.40
3.6
6.14
3.6
2.90
3.6
1.41
3.6
SW-4000M-PMCL
//
//
F
//
Period from
Data
EEN Falling
invalid time
to LVAL
(CLK)
rising (μs)
[E]
[D]
17.9
10
17.8
17
17.8
10
17.8
18
17.9
7
17.8
12
17.8
8
17.8
12
17.9
5
17.8
9
17.8
6
17.8
10
17.9
3
17.8
5
17.8
4
17.8
6
17.9
3
17.8
4
17.8
3
17.8
16
Data
valid time
(CLK)
[F]
2048
2048
2048
2048
1364
1364
1364
1364
1024
1024
1024
1024
512
512
512
512
409
409
409
409
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