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Fault Reset Flow
7.2 Fault Reset Flow
The fault reset sequence of operation is triggered by the assertion of the ClkFwdRst_H
signal line. Figure 7–2 shows the fault reset sequence of operation. The reset state
machine is initially in RUN state. ClkFwdRst_H is asserted by the system, which
causes the state machine to transition to the WAIT_FAULT_RESET state.
The 21264/EV68A internally resets a minimum amount of internal state. Note the
effects of that reset on the IPRs in Table 7–5
Table 7–5 Effect on IPRs After Fault Reset
IPR
After Reset
PAL_BASE
Maintained (not reset)
I_CTL
Bit value = 3 (both Icaches are enabled)
PCTX[FPE]
Set
WRITE_MANY Cleared (That is, the WRITE_MANY chain is initialized and the Bcache is turned off.)
EXC_ADDR
Set to an address that is close to the PC
The 21264/EV68A then waits for ClkFwdRst_H to deassert twice:
•
One deassert to transition directly to the WAIT_ClkFwdRst1 state without perform-
ing any BiST
•
One deassert to initialize the clock forwarding interface
The 21264/EV68A then begins fetching code at PAL_BASE + 0x780.
Figure 7–2 shows the fault reset sequence of operation. In Figure 7–2, note the follow-
ing symbols for constraints and information:
Constraints:
A
Min = 1 FrameClk_x cycle
Information:
a
Approximately 264 GCLK cycles
b
Approximately 525 GCLK cycles for external framing clock to be sampled and captured
c
1 FrameClk_x cycle plus 2 GCLK cycles
e
Next FrameClk_x rising edge
f
3 FrameClk_x cycles
g
Approximately 264 GCLK cycles to prevent first command from appearing too early
Initialization and Configuration
7–8
.
21264/EV68A Hardware Reference Manual
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