Pin Descriptions - Compaq EV68A Hardware Reference Manual

Compaq microprocessor reference manual
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Bcache Port
Term
Ratio
rd_wr
wr_rd
The Relationship Between Write-to-Read — BC_WR_RD_BUBBLES and wr_rd
The following formulas calculate the relationship between the Cbox CSR
BC_WR_RD_BUBBLES and wr_rd:
wr_rd = (BC_WR_RD_BUBBLES – 1) * bcfrm
or
BC_WR_RD_BUBBLES = ((wr_rd + bcfrm – 1) / bcfrm) + 1
There is never a need to use a value of 0 or 1 for BC_WR_RD_BUBBLES.
If wr_rd = 4*ratio, then value 3 would be the minimum
BC_WR_RD_BUBBLES value when bcfrm = 2*ratio, and value 5 would be the
minimum BC_WR_RD_BUBBLES value when bcfrm = ratio.
There is a special case for ratio = 2.0 in single-data mode. In this case, the for-
mula is:
wr_rd = (BC_WR_RD_BUBBLES – 2) * bcfrm
The Relationship Between Read-to-Write — BC_RD_WR_BUBBLES and rd_wr
Use the following formula to calculate the value for the Cbox CSR
BC_RD_WR_BUBBLES that produces the minimum rd_wr restriction:
BC_RD_WR_BUBBLES = rd_wr – 6
Note that a value for BC_RD_WR_BUBBLES of zero really means 64 GCLK cycles.
In that case, amend the formula. For example, it is impossible to have rd_wr = 6 in
the 1.5x dual-data rate mode case.

4.8.4 Pin Descriptions

This section describes the characteristics of the Bcache interface pins.
Cache and External Interfaces
4–50
Description
The number of GCLK cycles per peak Bcache bandwidth transfer. For example, a
ratio of 2.5 means the peak Bcache bandwidth is 16 bytes for every 2.5 GCLK
cycles.
The minimum spacing required between the read and write indices at the data/tag
pins, expressed as GCLK cycles.
The minimum spacing required between the write and read indices at the data/tag
pins, expressed as GCLK cycles.
21264/EV68A Hardware Reference Manual

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