Clock Forwarding And System Clock Ratio Configuration - Compaq EV68A Hardware Reference Manual

Power-Up Reset Flow and the Reset_L and DCOK_H Pins
Table 7–2 Signal Pin Reset State (Continued)
Signal
SysAddOut_L[14:0]
SysAddOutClk_L
SysCheck_L[7:0]
SysData_L[63:0]
Clocks
ClkFwdRst_H
ClkIn_H
ClkIn_L
EV6Clk_H
EV6Clk_L
Miscellaneous
DCOK_H
PllBypass_H
Reset_L
SromClk_H
SromData_H
SromOE_L
In addition, as power is being ramped, Reset_L must be asserted — this allows the
21264/EV68A to reset internal state. Once the target voltage levels are attained, sys-
tems should assert DCOK_H. This indicates to the 21264/EV68A that internal logic
functions can be evaluated correctly and that the power-up sequence should be contin-
ued. Prior to DCOK_H being asserted, the logic internal to the 21264/EV68A is being
reset and the internal clock network is running (either clocked by the PLL VCO, which
is at a nominal speed, or by ClkIn_H, if the PLL is bypassed).
The reset state machine is in state WAIT_SETTLE.

7.1.2 Clock Forwarding and System Clock Ratio Configuration

When DCOK_H is asserted, the 21264/EV68A samples several pins and latches in
some initialization state, including the value of the PLL Y
the ratio of the system clock to the internal clock (see Section 7.11.2.3), and enables the
charge pump on the phase-locked loop.
Initialization and Configuration
7–4
Reset State
Initially, during power-up reset, state
is not defined. If not during power-
up, preserves previous state. Then,
after the clock forward reset period
(as the external clocks start), signal
driven to NZNOP until the reset
state machine enters RUN, when it
is driven to NOP.
Tristated
Tristated
Tristated
NA (input)
NA (input)
NA (input)
Must be deasserted until dc voltage
reaches proper operating level.
NA (input)
NA (input)
Tristated
NA (input)
Tristated
Signal
SysDataOutValid_L
SysFillValid_L
SysVref
FrameClk_x
PLL_VDD
Tck_H
Tdi_H
Tdo_H
TestStat_H
Tms_H
Trst_L
divisor, which specifies
div
21264/EV68A Hardware Reference Manual
Reset State
NA (input)
NA (input)
NA
(I_DC_REF)
NA (input)
NA
(I_DC_REF)
NA (input)
NA (input)
Unspecified
Tristated
NA (input)
NA (input)