Performance Counter Control Register - Pctr_Ctl; Performance Counter Control Register; Performance Counter Control Register Fields Description - Compaq EV68A Hardware Reference Manual

Table 5–14 Process Context Register Fields Description (Continued)
Name
FPE
PPCE
Reserved
5.2.22 Performance Counter Control Register – PCTR_CTL
The performance counter control register (PCTR_CTL) is a read-write register that
controls the function of the performance counters for either aggregate counting or Pro-
fileMe sampling counting.
Usage of PCTR_CTL in performance monitoring is described in Section 6.10.
Figure 5–25 shows the performance counter control register.
Figure 5–25 Performance Counter Control Register
63
SEXT(PCTR0_CTL[47])
PCTR0[19:0]
PM_STALLED
PM_KILLED_BM
PCTR1[19:0]
SL0
SL1[1:0]
VAL
TAK
Table 5–15 describes the performance counter control register fields.
Table 5–15 Performance Counter Control Register Fields Description
Name
SEXT(PCTR0_CTL[47]) [63:48] RO
21264/EV68A Hardware Reference Manual
Extent Type Description
[2] RW,1 Floating-point enable—if clear, floating-point instructions
generate FEN exceptions. This bit is set by hardware on
reset.
[1] RW Process performance counting enable.
Enables performance counting for an individual process
with counters PCTR0 or PCTR1, which are enabled by set-
ting PCT0_EN or PCT1_EN, respectively.
Performance counting for the entire system can be enabled
by setting I_CTL[SPCE]. See Section 5.2.15 for more infor-
mation.
See Section 6.10 for information about performance count-
ing.
[0] — —
48 47
Extent Type Description
When read, this field is sign extended from PCTR_CTL[47]. Writes
to this field are ignored.
28 27 26 25
Internal Processor Registers
Ibox IPRs
6 5 4 3 2 1 0
LK99-0034A
5–23