Write_Many Chain Write Transaction Example; Cbox Write_Many Chain Order - Compaq EV68A Hardware Reference Manual

•
The order of multibit vectors is [MSB:LSB], so the LSB is first bit in the Cbox
chain.
Table 5–25 describes the Cbox WRITE_MANY chain order from LSB to MSB.
Table 5–25 Cbox WRITE_MANY Chain Order
Cbox WRITE_MANY Chain
BC_VALID_MODE
INIT_MODE[0]
BC_SIZE[3:0]
BC_ENABLE[0]
BC_ENABLE
BC_SIZE[0:3]
1
BC_ENABLE
1
BC_ENABLE
1
BC_ENABLE
INVAL_TO_DIRTY_ENABLE[1]
ENABLE_EVICT
BC_ENABLE
INVAL_TO_DIRTY_ENABLE[0]
BC_ENABLE
BC_ENABLE
BC_ENABLE
SET_DIRTY_ENABLE[0]
INVAL_TO_DIRTY_ENABLE[0]
SET_DIRTY_ENABLE[2:1]
BC_BANK_ENABLE[0]
BC_SIZE[0:3]
INIT_MODE
BC_WRT_STS[0:3]
1
MBZ during initialization mode; see Section 7.6 for information.
Figure 5–37 shows an example of PALcode used to write to the WRITE_MANY chain.
Figure 5–37 WRITE_MANY Chain Write Transaction Example
;
; Initialize the Bcache configuration in the Cbox
;
; BC_VALID_MODE = 1
; BC_ENABLE = 1
21264/EV68A Hardware Reference Manual
Description
Control Bcache block parity calculation
Enable initialize mode
Bcache size
Enable the Bcache
Duplicate CSR
Duplicate CSR
Duplicate CSR
Duplicate CSR
Duplicate CSR
WH64 acknowledges
Enable issue evict
Duplicate CSR
WH64 acknowledges
Duplicate CSR
Duplicate CSR
Duplicate CSR
SetDirty acknowledge programming
Duplicate CSR
SetDirty acknowledge programming
Enable bank mode for Bcache
Duplicate CSR
Duplicate CSR
Write status for Bcache in initialize-mode
(Valid, Dirty, Shared, Parity)
Cbox CSRs and IPRs
For Information:
Section 8.8
Section 7.6
Table 4–42
Table 4–42
Table 4–42
Table 4–42
Table 4–42
Table 4–42
Table 4–42
Table 4–15
Table 4–1
Table 4–42
Table 4–15
Table 4–42
Table 4–42
Table 4–42
Table 4–16
Table 4–15
Table 4–16
Section 4.8.5
Table 4–42
Section 7.6
Section 7.6
Internal Processor Registers
5–39