Nonexistent Memory Processing; Wrap Order For Double-Pumped Data Transfers - Compaq EV68A Hardware Reference Manual

System Port
Table 4–30 Wrap Interleave Order (Continued)
Sixth quadword
Seventh quadword
Eighth quadword
Table 4–31 defines the wrap order for double-pumped data transfers.
Table 4–31 Wrap Order for Double-Pumped Data Transfers
First quadword
Second quadword
Third quadword
Fourth quadword
Fifth quadword
Sixth quadword
Seventh quadword
Eighth quadword

4.7.9 Nonexistent Memory Processing

Like its predecessors, the 21264/EV68A can generate references to nonexistent (NXM)
memory or I/O space. However, unlike the earlier Alpha microprocessor implementa-
tions, the 21264/EV68A can generate speculative references to memory space. To
accommodate the speculative nature of the 21264/EV68A, the system must not gener-
ate or lock error registers because of speculative references. The 21264/EV68A trans-
lates all memory references through the translation lookaside buffer (TLB) and, in some
cases, the 21264/EV68A may generate speculative references (instruction execution
down mispredicted paths) to NXM space. In these cases, the system sends a SysDc
ReadDataError and the 21264/EV68A does the following:
•
Delivers an all-ones pattern to all load instructions to the NXM address
•
Force-fails all store instructions to the NXM address (much like a STx_C
failure)
•
Invalidates the cache block at the same index by way of an atomic Evict
command
Cache and External Interfaces
4–38
PA Bits [5:3] of Transferred QW
101 111
110 100
111 101
PA [5:3] of Transferred QW
x00 x01
x00 x01
x01 x00
x01 x00
x10 x11
x10 x11
x11 x10
x11 x10
001
010
011
x10
x10
x11
x11
x00
x00
x01
x01
21264/EV68A Hardware Reference Manual
011
000
001
x11
x11
x10
x10
x01
x01
x00
x00