Power Reset; System Reset - ST STM32C0 Series Getting Started

1.3.1

Power reset

A power reset is generated when one of the following events occurs:
• power-on reset (POR) or brown-out reset (BOR)
• exit from Standby mode
• exit from Shutdown mode
Power and brown-out reset set all registers to their reset values.
When exiting Standby mode, all registers in the V
V domain (back up register, WKUP, IWDG, and Standby/Shutdown mode control) are not impacted.
CORE
When exiting Shutdown mode, the brown-out reset is generated, resetting all registers.
1.3.2

System reset

System reset sets all registers to their reset values, except for the reset flags in the RCC control/status register 2
(RCC_CSR2) and the registers in the RTC domain.
System reset is generated when one of the following events occurs:
• low level on the NRST pin (external reset)
• window watchdog event (WWDG reset)
• independent watchdog event (IWDG reset)
• software reset (SW reset)
• low-power mode security reset
• option byte loader reset
• power-on reset
The reset source can be identified by checking the reset flags in the RCC_CSR2 register.
NRST pin (external reset)
Through specific option bits, the NRST pin is configurable to operate as:
• Reset input/output (default at device delivery)
Valid reset signal on the pin is propagated to the internal logic. Each internal reset source is led to a pulse
generator, whose output drives this pin. The GPIO functionality (PF2) is not available. The pulse generator
guarantees a minimum reset pulse duration of 20 μs for each internal reset source to be output on the
NRST pin. An internal reset holder option can be used, if enabled in the option bytes, to ensure that the
pin is pulled low until its voltage meets V
reset sources by external components when the line faces a significant capacitive load.
• Reset input
In this mode, any valid reset signal on the NRST pin is propagated to the device internal logic. Resets
generated internally by the device are not visible on the pin. In this configuration, GPIO functionality (PF2)
is not available.
• GPIO
In this mode, the pin can be used as PF2 standard GPIO. The reset function of the pin is not available.
Reset is only possible from device internal reset sources and it is not propagated to the pin.
AN5673 - Rev 2
domain are set to their reset value. Registers outside the
CORE
threshold. This function makes possible the detection of internal
IL
AN5673
Reset
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