Hsi48 Clock; Lse Clock; Lsi Clock - ST STM32C0 Series Getting Started

2.2

HSI48 clock

The HSI48 clock signal is generated from an internal 48 MHz RC oscillator.
The HSI48 RC oscillator has the advantage of providing a clock source at low cost (no external components). It
also has a startup time faster than the HSE crystal oscillator. However, even after calibration, it is less accurate
than an oscillator using a frequency reference such as quartz crystal or ceramic resonator.
The HSISYS clock derived from HSI48 can be selected as system clock after wake up from Stop mode. It can
also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails.
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. To
compensate for this variation, each device is factory calibrated at T
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Internal clock source calibration
register (RCC_ICSCR).
Voltage or temperature variations in the application may affect the HSI48 frequency of the RC oscillator. It can be
trimmed using the HSITRIM[6:0] bits in the Internal clock source calibration register (RCC_ICSCR).
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI48 RC is stable or not. At startup, the
HSI48 RC output clock is not released until this bit is set by hardware.
The HSI48 RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR).
The HSI48 signal can also be used as a backup source (auxiliary clock) if the HSE crystal oscillator fails.
2.3

LSE clock

The LSE crystal is a 32.768 kHz crystal or ceramic resonator. It has the advantage of providing a low-power but
highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in the Control register 1 (RCC_CSR1). The crystal
oscillator driving strength can be changed. It can be changed at runtime using the LSEDRV bit in the Control
register 1 (RCC_CSR1) to obtain the best compromise between low-power-consumption on one side, and
robustness and short startup time on the other side. The LSE drive can be decreased to its lower capability
(LSEDRV cleared) when the LSE is ON. However, once LSEDRV is selected, the drive capability cannot be
increased if LSEON = 1.
The LSERDY flag in the Control register 1 (RCC_CSR1) indicates whether the LSE crystal is stable or not. At
startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be
generated if enabled in the clock interrupt enable register (RCC_CIER).
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. This mode
is selected by setting the LSEBYP and LSEON bits in the AHB peripheral clock enable in the Sleep/Stop mode
register (RCC_AHBSMENR). The external clock signal (square, sinus, or triangle) with around 50% duty cycle
has to drive the OSCX_IN pin while the OSCX_OUT pin can be used as GPIO. See
2.4

LSI clock

The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby mode for the
independent watchdog (IWDG) and RTC. The clock frequency is 32 kHz. For more details, refer to the electrical
characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register 2 (RCC_CSR2).
The LSIRDY flag in the Control/status register 2 (RCC_CSR2) indicates if the LSI oscillator is stable or not. At
startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the
clock interrupt enable register (RCC_CIER).
AN5673 - Rev 2
= 25°C.
A
Figure 5.
AN5673
HSI48 clock
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