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Texas Instruments CI2EVM BoC Manuals
Manuals and User Guides for Texas Instruments CI2EVM BoC. We have
1
Texas Instruments CI2EVM BoC manual available for free PDF download: Quick Start Manual
Texas Instruments CI2EVM BoC Quick Start Manual (37 pages)
Dual EVM BoC Card
Brand:
Texas Instruments
| Category:
Motherboard
| Size: 1 MB
Table of Contents
Table of Contents
1
Overview
8
Introduction
8
Hardware Description
8
Figure 1 - Boc Top View
8
Figure 2: Front View, Assembled Boc
9
Figure 3 - Block Diagram
10
Hardware Configuration
11
Initial Installation Procedure
11
Default Jumper and Pin Settings
11
Boc Logic Power Source Selection [20]
11
Figure 4 - Boc Logic Power Source Selection
11
Table 1: Factory Configuration
11
EVM Power Source [16, 17, 18]
12
Figure 5: Boc Power Supply
12
Emulation Interface [1]
13
SGMII Interface
13
PCIE Interface
13
SRIO (Serial Rapidio) Interface
14
AIF (Antenna Interface) Interface
14
I2C Interface [5, 9, 11, 23]
14
Figure 6 - I2C Programming Header
14
Common REFCLK Source
15
REFCLK Oscillator Enable Header [19]
15
REFCLK Signal Levels
15
Table 2: JP5 & JP4 (Board a & B) I2C Switch Configuration
15
Table 3: JP10 REFCLK Enable Header
15
Figure 7: REFCLK Logic
16
Figure 8: REFCLK Biasing Components
16
Timer0 Output Headers [12, 22]
17
Timer0 Input Header [10, 24]
17
Common RP1CLK Source
17
RP1CLK Oscillator Enable Header [8]
17
RP1CLK Signal Levels
18
Figure 9: RP1CLK Logic
18
Table 4: JP1 RP1CLK Enable Header
18
Alternate RP1CLK Inputs [15]
19
Figure 10: RP1CLK Biasing Components
19
TCLK_B Signal Outputs [2, 13]
20
Figure 11: TCLK_B Interface
20
Table 5: JP2 TCLK_B Enable Header
20
TCLK_A Signal Outputs [2, 13]
21
Figure 12: TCLK_B Logic
21
Figure 13: TCLK_B Biasing Components
21
Common Pcierefclk Source [25]
22
Figure 14: TCLK_B Interface
22
Table 6: JP3 PCIEREFCLK Enable Header
22
Pcierefclk Logic
23
RP1FB Source [7]
23
RADSYNC & PHYSYNC Triggering [6]
23
Figure 15: RP1CLK Logic
23
Figure 16: RADSYNC & PHYSYNC Control
24
Figure 17: Cross Triggering Switch
24
Warnings and Cautions
25
Pin Assignment [Board A]
25
Table 7: RADSYNC / PHYSYNC Trigger Configuration
25
Table 8: AMC B+ Header Pin Assignment - Board a
25
Pin Assignment [Board B]
27
Table 9: AMC B+ Header Pin Assignment - Board B
27
Header Intra-Connections
29
Table 10: Serdes Board2Board Connections
29
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