I2C; External Memory Bus; Lcd - Digi ConnectCore 9C Hardware Reference Manual

A B O U T T H E M O D U L E S
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Interfaces
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I C 
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External Memory
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bus
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LCD

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ConnectCore 9C/Wi -9C Hardware Reference, Rev D 05/2010
4
– Odd, even, or no parity
– 5, 6, 7, or 8 bits
– 1 or 2 stop bits
– Receive-side character and buffer gap timers
Four receive-side data match detectors
Two dedicated DMA channels per module; 8 channels total
32 byte TX FIFO and 32 byte RX FIFO per module
2
I C v.1.0 configurable to master or slave
Bit rates: fast (400 kHz) or normal (100 kHz) with clock stretching
7-bit and 10-bit address modes
2
Supports I C bus arbitration
8-bit address bus
8-bit data bus
1 external chip select
Dual 64-deep, 32-bit wide FIFOs for buffering incoming display data
Support for color and monochrome single- and dual-panel for Super Twisted
Nematic (STN) displays with 4- or 8-bit interfaces
Support for Thin Film Transistor (TFT) color displays
Resolution up to 800 x 600 pixels
15 gray-level mono, 3375 color STN, and 64K color TFT support
– Patented gray-scale algorithm
1, 2, or 4 bits-per-pixel (bpp) palettized displays for mono STN
1, 2, 4, or 8 bpp palettized color displays for STN and TFT
16 bpp true-color non-palettized, for color STN and TFT
Programmable timing for different display panels
256 entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM
Frame, line, and pixel clock signals
AC bias signal for STN, data enable signal for TFT panels
Support for multiple data formats