Secondary Fifo Memory Map - Galil Motion Control DMC-1600 Series User Manual

Table of Contents

Enabling and Reading IRQ's

In order to service interrupts from the IRQ line, the IRQ control register (Status Byte) must first be

enabled. This is done by setting bit 6 of the control register (N+4) equal to "1".

When interrupted, first the interrupt routine must verify that the interrupt originated from the

DMC-1600 controller. This is done by checking that the IRQ enable and IRQ status bits (bit 5 and

6 of N+4) are high. The Status Byte can then be read by reading the IRQ register at N+8. The

returned Status Byte indicates what event generated the interrupt (for more information on specific

interrupt events, see the EI and UI commands in the Command Reference or the previous section

"Controller Event Interrupts..." in this chapter).

Once the Status Byte has been read, the interrupt must be cleared by writing a "1" to bit-5 of N+4.

Note: to preserve values of other bits, the interrupt service routine should read N+4 and write this

value back to N+4 to clear the interrupt.

Resetting the PC-to-DMC FIFO - To reset the output FIFO, write data to address N+8 where bit

2 is high and all other bits are low.

Resetting the DMC-to-PC FIFO - To reset the input FIFO, write data to address N+8 where bit 1

is high and all other bits are low.

Resetting the Controller - Clearing the FIFO is useful for emergency resets or Abort. For

example, to reset the controller, clear the FIFO, then send the RS command. If the controller is not

responding, it may be necessary to provide a hardware reset to the controller. This can be

accomplished by writing data to address N+8 where bit 7 is high.

Reset Register at N+8

Status Bit

Purpose

WRITE