Hardware Level Communications; Determining The Base Address; Communication Registers - Galil Motion Control DMC-1600 Series User Manual

Hardware Level Communications

This section of the chapter describes in detail the structures used to communicate with the controller at the register
interface level. The information in this section is intended for advanced programmers with extensive knowledge of
ISA and PCI bus operation.
For main bi-directional communication, the DMC-1600 features a 512 character write FIFO buffer, and a 512
character read buffer. This permits sending commands at high speeds ahead of their actual processing by the DMC-
1600. The DMC-1600 also provides a secondary FIFO, for access to the data record.
Note: This chapter provides an in-depth look at how the controller communicates over the PCI bus at the register
interface level. For most users, we recommend using the drivers supplied by Galil to provide the necessary tools for
communicating with the controller.

Determining the Base Address

The base address "N" is assigned its value by the BIOS and/or Operating System. The FIFO address N is referenced
in the PCI configuration space at BAR2 (offset 18H). The following PCI information (HEX) can be used to identity
the DMC-1600 controller:
PCI Device Identification
DEVICE ID
9050H
Read, Write, and Control Registers
The DMC-1600 provides four registers used for communication. The main communications FIFO register for
sending commands and receiving responses occupies address N. The control register used to monitor the main
communications status occupies address N+4. The reset register occupies address N+8 and is used for resetting the
controller and/or main read/write FIFO registers as well as retrieving the IRQ status byte. The secondary FIFO for
accessing the data record occupies address N+C.

Communication Registers

Register Address
Main FIFO
CONTROL
IRQ / RESET
Secondary FIFO
Simplified Communication Procedure
The simplest approach for communicating with the DMC-1800 is to check bits 0 and 2 of the
CONTROL register at address N+4. Bit 0 is for WRITE STATUS and bit 2 is for READ
STATUS.
Read Procedure - To receive data from the DMC-1800, read the control register at address N+4
and check bit 2. If bit 2 is zero, the DMC-1600 has data to be read in the READ register at
address N. Bit 2 must be checked for every character read.
DMC-1600
VENDOR ID SUBSYSTEM ID
10B5H
Read/Write
N Read / Write
N+4 Read / Write
N+8 Read / Write
N+C Read only
SUBSYSTEM VENDOR ID
1640H
Description
Send commands and receive responses
For FIFO status control
For IRQ status byte and controller reset
For data record access
Chapter 4 - Software Tools and Communications • 57
1079H