Taiwan Commate Computer Inc. PV-DDR User Manual page 28

When enabled, up to four D words of data can be written to the PCI bus
without interrupting the CPU. When disabled, a write buffer is not used
and the CPU read cycle will not be completed until the PCI bus signals
that it is ready to receive the data.
3.4.17 PCI Master 0 WS Write
When enabled, writes to the PCI bus are command with zero wait states.
3.4.18 PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
3.4.19 Memory Hole
Enabling this feature reserves 15MB to 16MB memory address space to
ISA expansion cards that specifically require this setting. This makes the
memory from 15MB and up unavailable to the system. Expansion cards
can only access memory up to 16MB.
3.4.20 System BIOS Cacheable
Allows the system BIOS to be cached for faster system performance.
3.4.21 Video BIOS Cacheable
Allows the video BIOS to be cached for faster video performance.
3.4.22 Video RAM Cacheable
Enabled allows caching of the video RAM, resulting in better system
performance. However, if any program writes to this memory area, a
system error may result.
3.4.23 Memory Parity / ECC Check
When Disabled, there will be no memory errors shown on the monitor for
Memory parity SERR# (NMI). When parity DRAM modules are used,
select Parity or ECC (Error Checking and Correcting) to correct 1 bit
memory errors in the memory.