Analog Devices dBCool ADT7473 Manual page 66

ADT7473
Table 34. Register 0x5C, Register 0x5D, and Register 0x5E—Configuration Register
Bit N me a
[2:0] SP IN
[3] SLOW
[4] INV
[7:5] BHVR
Table 35. TEM P T /PWM Frequency Registers
RANGE
1
R egister Address R/W
0x5F R/W
0x60 R/W
0x61 R/W
1
These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.
R/W Description
R/W These bits control the start-up timeout for PWMx. The PWM output stays high until two
valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during the
fan TACH measurement directly after the fan start-up
mea sure ment reads 0xFFFF and In
minimum high and low bytes contain 0xFFFF or 0x0000, then the Interrupt Status Register
2 bit is not set, ev
000 = No start-up t
001 = 10 0 ms.
010 = 250 ms (default).
011 = 40 0 ms.
100 = 66 7 ms.
101 = 1 s ec.
110 = 2 s ec.
111 = 4 sec.
R/W SLOW = 1 makes the ramp rates for acoustic enhancement four times longer.
R/W This bit inverts the PWM output. The default is 0, which corre
for 100% duty cycle. Setting this bit to 1 inverts t
corresponds to a logic low output.
R/W These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 temperatur
001 = Local temperature controls PWM
010 = Remote 2 temperature controls PWMx (automatic fan control mode).
011 = PWMx runs full speed.
100 = PWMx disabled (de
101 = Fastest speed calculated by local a
110 = Fastest speed calculated by all three temperature channel controls PWMx.
111 = Manual mode. PWM duty cycle registers (Register 0x30 to Register 0x32) become
writable.
Description
Remote 1 T /PWM1 frequency.
RANGE
Local temperature T
Remote 2 T /PWM3 frequency.
RANGE
s (Power-On Default = 0x82)
terrupt Status Register 2 reflects the fan fault. If the TACH
en if the fan has not star
imeout.
e controls PWMx (automatic fan control mode).
x (automatic fan control mode).
fault).
nd Remote 2 temperature controls PWMx.
/PWM2 frequency.
RANGE
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timeout period, then the TACH
ted.
sponds to a logic high output
he PWM output, so 100% duty cycle
Power-On Default
0xCC
0xCC
0xCC