Analog Devices dBCool ADT7473 Manual page 28

ADT7473
The fan inputs have an input resistance of nominally 160 k Ω
ground, which should be taken into account when calculati
resistor values.
With a pull-up voltage of 12 V and pull-up resistor less than
1 kΩ, suitable values for R1 and R2 are 120 kΩ and 47 kΩ,
respectively. This gives a high input voltage of 3.35 V.
12V
<1kΩ
R1*
TACH
OUTPUT
Figure 40. Fan with Strong TACH Pull-Up to > V
Attenuated with R1/R2
Fan Speed Measurement
The fan counter does not count the fan TACH output pulses
directly, because the fan speed could be less th
and it would take several s econds to accumulate a reasonably
large and accurate count. Instead, the period of the fan revolu-
tion is measured by gating an on-chip 90 kHz oscillator into th
input of a 16-bit counter for N periods of the fan TACH o
(see Figure 41), so the accumulated count is actually
proportional to the fan tachometer period, and inversely
proportional to the fan speed.
N, the num ber of pulses counted, is determined by the settings
of the TACH pulses per revolution register
This register contains two bits for each fan,
(default), three, or four TACH pulses to be
CLOCK
PWM
TACH 1
2
3
4
Figure 41. Fan Speed Measurement
Fan Speed Measurement Registers
The fan tachometer readings are 16-bit values consisting of a
2-byte read from the ADT7473.
ng
V
CC
TACH
FAN SPEED
COUNTER
R2*
ADT7473
*SEE TEXT
or Totem-Pole Output,
CC
an 1,000 RPM
utput
(Register 0x7B).
allowing one, two
counted.
Rev. A | Page 28 of 76
to
Register 0x28, TACH1 Low Byte = 0x00 de
Register 0x29, TACH1 High Byte = 0x00 default
Register 0x2A, TACH2 Low Byte = 0x00 default
Register 0x2B, TACH2 High Byte = 0x00 default
Register 0x2C, TACH3 Low Byte = 0x00 default
Register 0x2D, TACH3 High Byte = 0x00 default
Regist er 0x2E, TACH4 Low Byte = 0x00 defa
Regist er 0x2F, TACH4 High Byte = 0x00 defa
Reading F an Speed from the ADT7473
The measurem ent of fan speeds involves a 2-register read for
each measurement. The low byte should be read first. This
causes the high byte to be frozen until both high and low byte
registers have been read, preventing erroneous TACH read
The fan tachometer reading registers report back the number
11.11 μs period clocks (90 kHz oscillator) gated to the fan sp
counter, from the rising edge of the first fan TACH pulse to t
rising edge of the third fan TACH pulse (assuming two pulses
e
per revolution are being counted). Because the device is
essentially measuring the fan TACH
count value, the slower th
tachometer reading of 0x
stalled or is running very slowly (<100 RPM).
High Limit > Comparison Performed
Because the actual fan TACH period is measured, falling
a fan TACH limit by 1 sets the appropriate status bit and can
used to generate an SMBALERT .
Measuring Fan TACH
When the ADT7473 starts up, TACH measurements are locked.
In effect, an internal read of the low byte has been ma
each TACH input. The net result of th
read ings are locked until the hig
corres ponding TAC
also i gnored until th
Once the correspondi
meas urements are u
norm al.
Fan TACH Limit
The fan TACH limi
byte s.
Register 0x54, TACH1 Minimum Low Byte = 0xFF default
Register 0x55, TACH1 Minimum High Byte = 0xFF default
Register 0x56, TACH2 Minimum Low Byte = 0xFF default
fault
ult
ult
period, the higher the
e fan is actually running. A 16-bit fan
FFFF indicates either the fan has
is is that all TACH
h byte is read from the
H registers. Al l TACH related interrupts are
e appropriate high byte is read.
ng hig h byte has been read, TACH
nlocked and interrupts are processed as
Registers
t registers are 16-bit values consisting of two
ings.
of
eed
he
below
be
de for