Read Operations; Smbus Timeout; Voltage Measurement I Nput; Analog-To-Digital Converter - Analog Devices dBCool ADT7473 Manual

READ OPERATIONS

The ADT7473 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly r
register. The reg iste r address must have been pre
In this operation, the master device receives a
slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-b
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a s top condition on SDA, and the
transaction ends.
In the ADT7473, the receive byte protocol is us
single byte of data from a register whose address has previously
been set by a send byte or write byte operation. This opera
is illustrated in Figure 19.
1 2
SLAVE
S R
ADDRESS
Figure 19. Single-Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT . One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device's SMBALERT line goes low, the following
events occur:
•
SMBALERT is pulled low.
•
The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
•
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
•
If more than one device's SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
eading a single
viously set up.
single byte from a
it slave address followed by the
ed to read a
tion
3 4 5 6
A DATA A P
Once the ADT7473 has responded to t
the master must read the status registers, and the SMBALERT is
cleared only if the error condition is gone.

SMBus TIMEOUT

The ADT7473 includes an SMBus timeout feature. If there is n
SMBus activity for 35 ms, the ADT7473 ass
locked and releases the bus. This prev
locking or holding the SMBus expecting data. Some SMBus
controllers cannot work with the SMBus timeout feature, so it
can be disabled.
Configuration Register 1 (0x40)
Bit 6 TODIS = 0; SMBus timeout enabled (default)
Bit 6 TODIS = 1; SM
VOLTAGE MEASU
The ADT7473 has one external vol
and c an also measure its own supp
meas ure V . The V
CCP
out t hrough the V
mon itor a chipset supply voltage in
ANALOG-TO-DIGITAL CONVE
All analog inputs are mu
approximation, analog-to-digital co
tion of 10 bits. The basic input rang
input has built-in attenuators to allow m
without any external components. To allow for th
the supply voltage, the ADC produces an output o
(768 decimal or 300 hex) for the nominal input voltage and thus
has adequate headroom to deal with overvoltages.

INPUT CIRCUITRY

The internal structure for the V
Figure 20. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first order
low-pass filter that gives the input immunity to high frequency
noise.

VOLTAGE MEASUREMENT REGISTERS

Register 0x21 V
Register 0x22 V
Rev. A | Page 13 of 76
he alert response address,
umes the bus is
ents the device from
Bus timeout disabled
REMENT I NPUT
tage m easurement channel
ly vo ltage, V
supply volt age measurement is carrie
CC
pin (Pin 3). Th e V input can be
CC CCP
computer systems.
RTER
ltiplexed into the on-chip, successive
nverter. This has a resolu-
e is 0 V to 2.25 V, but the
easurement of V
analog input is shown in
CCP
17.5kΩ
V
CCP
52.5kΩ 35pF
Figure 20. Structure of Analog Inputs
Reading = 0x00 default
CCP
Reading = 0x00 default
CC
ADT7473
o
. Pin 14 can
CC
d
used to
CCP
e tolerance of
f ¾ full scale