Fan Presence Detect; Sleep States; Xnor Tree Test Mode; Power-On Default - Analog Devices dBCool ADT7473 Manual

By reading the PWMx current duty cycle registers, the user ca
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode. See the Programming the
Automatic Fan Speed Control Loop section for details.

FAN PRESENCE DETECT

This feature can be used to determine if a 4-wire fan is dir
connected to a PWM output. This feature does not work for
3 -wire fans. To detect whether a 4-wire fan is connected directly
to a PWM output, the following steps must be performed in this
order:
1. Drive the appropriate PWM outputs to 100% duty cycle.
2. Set Bit 0 of Configuration Register 2 (0x73).
3. Wait 5 ms.
4. Program the fans to run at a different speed if necessary.
5. Read the state of Bits [3:1] of Configuration
Register 2 (0x73). The state of these bits reflects whether a
4-wire fan is directly connected to the PWM output.
As the detection time only takes 5 ms, programming the PWM
outputs to 100% and then back to their normal speed is not
noticeable in most cases.
Description of How Fan Presence Detect Works
Typical 4-wire fans have an internal pull up to 4.75 V ± 10%,
which typically sources 5 mA. While the detection cycle is on,
an internal current sink is turned on, sinking current from the
fan's internal pull-up. By driving some of the current from the
fan's internal pull-up (~100 µA) the logic buffer switches to a
defined logic state. If this state is high, a fan is present; if it is
low, no fan is present.
The PWM input voltage should be clamped to 3.3 V. This
ensures the PWM output is not pulled to a voltage higher than
the maximum allowable voltage on that pin (3.6 V).

SLEEP STATES

The ADT7473 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor is lowered in these states. If
using the dynamic T mode, lowering the core voltage of the
MIN
processor changes the CPU temperature and the dynamics of
the system under dynamic T
monitoring THERM , the THERM timer should be disabled
during these states.
control. Likewise, when
MIN
n
Dynamic T
MIN
Bit [1] VCCPLO = 1
When the V
following occurs:
1. Status Bit 1 (V
2. SMBALERT
ectly
3. THERM
should hold its value prior to the S3 or S5 state.
4. Dynamic T
being adjusted due to an S3 or S5 state.
5. The ADT7473 is prevented from entering the shutdown
state.
Once the core voltage, V
everything is re-enabled, and the system resumes normal
operation.

XNOR TREE TEST MODE

The ADT7473 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XNOR tree, it is
possible to detect opens or shorts on the system board.
Figure 42 shows the signals that are exercised in the XNOR tree
test mode. The XNOR tree test is invoked by setting Bit 0
(XEN) of the XNOR tree test enable register (0x6F).

POWER-ON DEFAULT

When the ADT7473 is powered up, it polls the V
If V stays below 0.75 V (the system CPU power rail is not
CCP
powered up), the ADT7473 assumes the functionality of the
default registers after the ADT7473 is addressed via any valid
SMBus transaction.
Rev. A | Page 31 of 76
Control Register 1 (0X36)
voltage drops below the V
CCP
) in Status Register 1
CCP
is generated, if ena bled.
monitoring is disabled. The THERM timer
control is disabled. This prevents T
MIN
, goes above the V
CCP
TACH1
TACH2
TACH3
TACH4
PWM2
PWM3 PWM1/XTO
Figure 42. XNOR Tree Test
ADT7473
low limit, the
CCP
is set.
from
MIN
low limit,
CCP
input.
CCP