Analog Devices dBCool ADT7473 Manual page 70

ADT7473
Table 42. THERM Limit Registers
Register Address
0x6A
0x6B
0x6C
If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the
1
system in the event of a critical over temperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is
disabled. The PWM output remains at 100% until the temperature drops below THERM Limit − Hysteresis. If the THERM pin is programmed as an output, then
exceeding these limits by 0.25°C can cause the THERM pin to assert low as an output.
2 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.
Table 43. Temperature/T
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Register Address Bit Name
0x6D
HYSL [3:0]
HYSR1 [7:4]
0x6E
HYSR2 [7:4]
1 Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its T
value, the fan remains running at PWM
The hysteresis value chosen also applies to that temperature channel, if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the THERM
limit is exceeded and remains at 100% until the temperature drops below THERM – hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be
programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to T
2 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.
Table 44. XNOR Tree Test Enable Register
Register Address Bit Name
0x6F
XEN [0]
Reserved
[7:1]
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 45. Remote 1 Temperature Offset Register (0x70)
1
Bit R/W
[7:0] R/W
1 This register becomes read only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 46. Local Temperature Offset Register (0x71)
1
Bit R/W
[7:0] R/W
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
1
2
R/W Description
R/W Remote 1 THERM limit.
R/W
Local THERM limit.
R/W Remote 2 THERM limit.
1
Hysteresis Registers
2
R/W Description
R/W Remote 1 and local temperature hysteresis.
Local temperature hysteresis. 0°C to 15°C of hysteresis can be
applied to the local temperature AFC and dynamic T
control loops.
Remote 1 temperature hysteresis. 0°C to 15°C of hysteresis
can be applied to the Remote 1 temperature AFC and
dynamic T
R/W Remote 2 temperature hysteresis.
Local temperature hysteresis. 0°C to 15°C of hysteresis can be
applied to the local temperature AFC and dynamic T
control loops.
duty cycle until the temperature = T
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1
R/W Description
R/W XNOR tree test enable register.
If the XEN bit is set to 1, the device enters the XNOR tree test
mode. Clearing the bit removes the device from the XNOR tree
test mode.
Unused. Do not write to these bits.
Description
Allows a twos complement offset value to be automatically added to or
subtracted from the Remote 1 temperature reading. This is to compensate for
any inherent system offsets such as PCB trace resistance. LSB value = 0.5°C.
Description
Allows a twos complement offset value to be automatically added to or
subtracted from the local temperature reading. LSB value = 0.5°C.
control loops.
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– hysteresis. Up to 15°C of hysteresis can be assigned to any temperature channel.
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Rev. A | Page 70 of 76
Power-On Default
0xA4 (100°C)
0xA4 (100°C)
0xA4 (100°C)
Power-On Default
0x44
MIN
0x40
MIN
.
MIN
Power-On Default
0x00
Power-On Default
0x00
Power-On Default
0x00
MIN