Analog Devices dBCool ADT7473 Manual page 63

Table 24. Register 0x37—Dynamic
Bit Name R/W Description
[2:0] CYR1 R/W 3-bit remote 1 cycle value. The
the cont
thermal time constants that ne
Bits Decreas
000 8 cycles (1 sec)
001 16 cycles (2 sec)
010 32 cycles (4 sec)
011 64 cycles (8 sec)
100 128 cycles (16 sec)
101 256 cycles (32 sec)
110 512 cycles (64 sec)
111 1024 cycles (128 sec)
[5:3] CYL R/W 3-bit loca
adjustm
system h
control l
Bits Decreas
000 8 cycles (1 sec)
001 16 cycles (2 sec)
010 32 cycles (4 sec)
011 64 cycles (8 sec)
100 128 cycles (16 sec)
101 256 cycles (32 sec)
110 512 cycles (64 sec)
111 1024 cycles (128 sec)
[7:6] CYR2 R/W 2 LSBs of 3-bit remote 2 cycle value
(Register 0x36). These three
loop for
constant
Bits Decreas
000 8 cycles (1 sec)
001 16 cycles (2 sec)
010 32 cycles (4 sec)
011 64 cycles (8 sec)
100 128 cycles (16 sec)
101 256 cycles (32 sec)
110 512 cycles (64 sec)
111 102 4 cycle
1
This register becomes read-only when th
Table 25. Maximum PWM Duty Cycle
R egister Address R/W
0x38 R/W
0x39 R/W
0x3A R/W
1 These registers set the maximum PWM duty cyc
2
These registers become read-only when the Configuration Regis
of Configuration Register 4 (0x7D) is set, then on a THERM
3 If Bit 3
If Bit 3 of Configuration Register 4 (0x7D) is 0, then on a THERM overtemperature event, fans go to 100% PWM.
T Control Register 2 (Power-On Default = 0x00)
MIN
se three bits de
rol loo p for the Remot e 1 channel, in te
ed to be foun
e Cycl e
l tem perature cycl e value. These three bits define
ents in the control l oop for the local temperature c
as ass ociated therm al time constants that need to be
oop.
e Cycl e
. The MSB of the 3-bit c
bits define the delay time be
the Re mote 2 chan nel, in terms of number of mo
s that n eed to be fo und to optimize the respons
e Cycl e
s (128 sec)
e Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this regis
Registers (Power-On Default = 0xFF)
2 Description
Maximum duty cycle for PWM1 output, default = 100% (0xFF).
Maximu m duty cycle
Maximu m duty cycle for PWM
le of t he PWM out put.
ter 1 lock bit is set to 1. Any
overtemperature event, fans go to their maximum programmed PWM value as programmed here.
fine the delay time between making s
rms of number of monitoring cycles
d to optimize the response of fans and
Increase Cycle
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
10 24 cycles (128 sec)
20 48 cycles (256 sec)
the delay time between making subsequent T
hannel, in terms of number of monit
found to optimize the response o
Inc rease Cycle
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
ode resides in Dynamic T
tween making subsequent T
nitoring cycles. The system has associa
e of fans and the control loop.
Increase Cycle
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
1, 2, 3
for PWM2 output, default = 100
3 output, default = 100% (0xFF).
subsequent attempts to wr
Rev. A | Page 63 of 76
1
ubsequen t T
MIN
. The sy stem has associated
the con trol loop.
oring c
f fans
Contro l Re
MIN
adjustm
MIN
ted th
ter fail.
% (0xFF).
ite to th is register fail.
ADT7473
adjustments in
MIN
ycles. The
and the
gister 1
ents i n the control
ermal time