Analog Devices dBCool ADT7473 Manual page 24

ADT7473
If the THERM timer value exceeds the THERM timer limit
value, the F4P bit (Bit 5) of Interrupt Status Register 2 is set and
an SMBALERT is generated. The F4P bit (Bit 5) of Interrupt
Mask Register 2 (0x75) masks out the SMBALERT if this bit is
set to 1; however, the F4P bit of Interrupt Status Register 2 still
is set if the THERM timer limit is exceeded.
Figure 30 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (0x7A) causes an SMBALERT to be
generated on the first THERM assertion. A THERM timer limit
value of 0x01 generates an SMBALERT once cumulative
THERM assertions exceed 45.52 ms.
Configuring the THERM Behavior
1. Configure Pin 9 as a THERM timer input.
Setting Bit 1 ( THERM timer enable) of Configuration
Register 3 (0x78) enables the THERM timer monitoring
functionality. This is disabled on Pin 9 by default.
Setting Bit 0 and Bit 1 (PIN9FUNC) of Configuration
Register 4 (0x7D) enables THERM timer/out
functionality on Pin 9 (Bit 1 of Configuration
THERM , must also be set). Pin 9 can also be used as
TACH4.
Setting Bit 5, Bit 6, and Bit 7 of Configuration Register 5
(0x7C) makes THERM bidirectional. This means that if th
appropriate temperature channel exceeds the
temperature limit, the THERM output asserts. If the
ADT7473 is not pulling THERM low, but THERM is
pulled low by an external device (such as a CPU
overtemperature signal), the THERM timer also times
THERM assertions.
If Bit 5, Bit 6, and Bit 7 of Configuration Register 5 (0x7C)
are set to 0, THERM is set as a timer input only.
2.
3.
4.
put
Register 3,
5.
e
THERM
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Select the desired fan behavior for THERM timer events.
Assuming the fans are running, setting Bit 2 (BOOST) of
Configuration Register 3 (0x78) causes all fans to run at
100% duty cycle whenever THERM is asserted. This allows
fail-safe system cooling. If this bit is 0, the fans run at their
current settings and are not affected by THERM events. If
the fans are not already running when THERM is asserted,
the fans do not run at full speed.
Select whether THERM timer events should generate
SMBALERT interrupts.
Bit 5 (F4P) of Interrupt Mask Register 2 (0x75), when set,
masks out the SMBALERT when the THERM timer limit
value is exceeded. This bit should be cleared if SMBALERT
is based on THERM events are required.
Select a suitable THERM limit value.
This value determines whether an SMBALERT is generated
on the first THERM assertion, or only if a cumulative
THERM assertion time limit is exceeded. A value of 0x00
causes an SMBALERT to be generated on the first THERM
assertion.
Select a THERM monitoring time.
This value specifies how often OS or BIOS level software
checks the THERM timer. For example, BIOS could read
the THERM timer once an hour to determine the cumula-
tive THERM assertion time.
If, for example, the total THERM assertion time is
<22.76 ms in Hour 1, >182.08 ms in Hour 2, and >5.825
sec in Hour 3, this can indicate that system performance is
degrading significantly because THERM is asserting more
frequently on an hourly basis.
Alternatively, OS- or BIOS-level software can timestamp
when the system is powered on. If an SMBALERT is
generated due to the THERM timer limit being exceeded,
another timestamp can be taken. The difference in time
can be calculated for a fixed THERM timer limit time. For
example, if it takes one week for a THERM timer limit of
2.914 seconds to be exceeded and the next time it takes
only one hour, this is an indication of a serious degradation
in system performance.