Fluke 6080A Service Manual page 142

TROUBLESHOOTING AND REPAIR
FREQUENCY SYNTHESIS
Next, use the low impedance probe to check the signal at the input to the divider (U58)
at pin 15. There should be a -15 dBm lower sideband signal as measured on the
spectrum analyzer. A problem at this point indicates a problem in the low order digits
generator (U21, U22, U23, U60, U61), active quadrature generator (U59), the SSB
mixer (U53, U54), or the divider input amplifier (U55).
Program the signal generator to 804.000500 MHz. The signal at the output of the triple
modulus prescaler, TP33, should be an approximately 15-MHz TTL signal. The signal
at the output of the N-divider gate array, TP34, should be approximately 1 MHz. As
the 1-MHz digit is programmed, this frequency should change, since the divide ratio is
changing.
To troubleshoot the low order digit generator, check the signal at TP3 and TP4. There
should be a 25% duty cycle, active high 20-MHz TTL signal. Program the signal
generator to 800.000000 MHz. The signal at TP5 should be 10 MHz TTL. As you
program the UUT to 1 Hz, 10 Hz, and 100 Hz digits, the frequency at TP5 should
change by 20 kHz, 200 kHz, and 2 MHz, respectively. When the UUT is programmed
to 800.000499 MHz, the frequency at TP5 should be 19.98 MHz. The outputs of the
two divide-by-10, U60, U61 should be 1.998 MHz and 19.98 kHz, respectively. The
output of the active quadrature generator, U59, at TP37 and TP38 should be
approximately 450-mV p-p 19.98-kHz sine waves.
Monitor the frequency at TP21 as you tune the power supply. If the frequency is below
240 MHz, the frequency at TP21 should be below 1 MHz. There should be a TTL
signal at TP24 that is predominantly low with very thin pulses going high. There
should be a similar signal at TP25, except the "low" voltage is approximately -0.5V and
the "high" voltage is +2.8 V. The voltage at TP40 should be about 28V. If the frequency
is above 240 MHz, the frequency at TP21 should be above 1 MHz. The signal levels at
TP24 and TP25 should be predominantly high. The voltage at TP40 should be about
-2V. If the signals at TP24 and TP25 are correct, but the voltage at TP40 does not
change from approximately -2V to +28V as the frequency at TP21 is adjusted above
and below 1 MHz, the problem is probably in the loop amplifier (U34, etc.), the current
source (U63, etc.), the switching diodes (CR18, CR19), or the KN DAC (U6, U7, etc.).
The loop should lock when you reconnect the shorting jumper between TP40 and
TP41. If the loop doesn't lock, the final circuitry to check is the low-pass filter (L56,
L57, etc.), the clamp circuit (U35, U36, etc.), and the lead-lag network. FET Q10
should be on (~+5 V on the gate) below a undivided Sub-Synthesizer frequency of 230
MHz and off (~0V on the gate) above 230 MHz. You can disable the clamp circuit by
disconnecting CR20 and CR21.
To check the various DACs, program the UUT to SPCL 943. This sets all the DACs at
full scale. The voltage at the output of the KN DAC (TP35), REFVOL DAC (TP39)
and STEERING DAC (TP6) should be approximately 10.23V. With the UUT
programmed to SPCL 942, which sets the DACs to half scale, the voltages should be
about 5.12V.
6C-12