Fluke 6080A Service Manual page 153

in the 1-, 2-, 5-MHz external reference mode (SPCL 761), REFSEL should be a logic
low. The signal at U503 pin 11 will be 1, 2, or 5 MHz (typically 5 MHz as configured at
the factory), depending on how SW502 is set. The setting of this switch is described in
the alignment section.
If the voltage at TP19 is approximately -13V when in internal reference, first check the
internal TCXO. There should be a 10-MHz TTL signal at U502 pin 12 and U503 pin 3.
Power to the TCXO is supplied from Q501 at TP18. To check the external reference,
connect a 10-MHz source, +4 dBm signal to the 10-MHz REF IN. There should be a 1V
p-p sine wave at J6. There should be a 10-MHz TTL signal at U510 pins 9 and 11 and
eventually at U503-5. The logic control for the reference section is summarized below:
STATE
External 10 MHz
External 5 MHz
External 2 MHz
External 1 MHz
Internal TCXO
x = 1 if normal 10 MHz external; 0 if SPCL 761 (1, 2, or 5, MHz external reference).
At this point there should be 10-MHz signals at U503 pins 3 and 11. To check the phase
detector, remove the jumper between TP20 and TP21. Connect a variable power
supply to TP21. Monitor the frequency at U503 pin 11. As you swing the power supply
from about 1 to 10V, the frequency at TP11 should move below and above 10 MHz by
about ± 200-500 Hz. The voltage at TP19 should range between -13 and +13V.
Reconnect the jumper between TP20-TP21.
The last circuitry to check is the out-of-lock circuitry (U509, U512, U515). With the
control voltage between 1 to 11V, the signal at J2-2 should be a TTL logic high.
To troubleshoot the 80-MHz doubler section, first check the bias voltages. At the
junction of R648, C652, and T601 the voltage should be about 8.8V. The voltage at the
collector of Q610 should be about 8.1V. The ac voltage on the collector of Q609 should
be 40-MHz, 2.7V p-p . There should be an 80-MHz full-wave rectified signal 1.2V p-p
at the output of the doubler (CR601, CR602). At J5, there should be a 80-MHz 0.8V
p-p sine wave.
MAIN LOOP
A status code 243 indicates the coarse loop is out of lock. A status code 244 or possibly
245, which indicates the sum loop is out of lock, could possibly be caused by a marginal
lock condition in the coarse loop.
The first thing to check is the coarse loop steering circuit. Program the UUT to 544
MHz, which programs the coarse loop to 640 MHz. Connect the output of the Coarse
Loop VCO, A2-J8, to a spectrum analyzer. Ground the phase lock port, TP7 and
disable the search oscillator by moving the jumper from TP13 to TP28-TP13. There
should be a signal at 640 MHz ± 2 MHz. If the signal is absent or is far off frequency,
either the Coarse Loop VCO or the VCO steering voltage circuit is faulty. The steering
voltage circuit can be checked by programming the UUT with SPCL 943, and
measuring the DC voltage at TP8, the VCO steering port. This special function
programs the steering DAC to full scale, and should result in a reading of 24V. If the
Coarse Loop VCO seems to function properly, the Coarse Loop PCA is probably
faulty.
EXTREFH TCXOH REFSEL
1 1
1 1
1 1
1
1
1
0
TROUBLESHOOTING AND REPAIR
Q502 Q506
1 on(+5V) on(+15V)
0 on on
0 off(0V) on
off
0 on
on on
X*
FREQUENCY SYNTHESIS
6C-23