Fluke 6080A Service Manual page 138

TROUBLESHOOTING AND REPAIR
FREQUENCY SYNTHESIS
The N-divider gate array includes a two-decade rate multiplier that produces the
fractional part of the division. The N-divider gate array rate multiplier produces a
pulse train with a programmed number of pulses for a 100-cycle frame of the 1-MHz
N-divider output.
The programmed number ranges between zero and 99, corresponding to 10-kHz steps
at the VCO frequency. The flip-flops in the rate multiplier get set up on count 29, and
on count 30 a pulse may or may not be present, depending on the programming of the
rate multiplier. This is the shaded pulse in the timing diagram (Figure 6C-5).
Irregularly spaced rate-multiplier pulses cause the mode line to go low, and the
prescaler divides by P+l at a rate equal to the rate multiplier programming.
A 16/17 dual-modulus prescaler will not allow division from 160 to 320 without holes.
For example, 170 is ten frames of 17. Consequently, there is no place to slip in the
rate-multiplier pulses. It is not possible to divide by 171.
By using a triple-modulus prescaler, these problems are solved. Continuing with the
previous example, 170 is 10 frames of 17 and 0 frames of 18. The deleter allows the
prescaler to divide by 18 at a rate equal to the rate-multiplier frequency. Number 171 is
9 frames of 17 and 1 frame of 18. A software algorithm determines whether to operate
in the 16/17 mode (TRMODL=1) or 17/18 mode (TRMODL=0).
The frequency at the output of the N-divider gate array is (Fo - Fs - Fd)/N. Since this
must be equal to reference frequency, Fr, and Fr is 1 MHz, the VCO frequency is Fo =
N + Fs + Fd, where Fs is the SSB audio frequency from the low order digit generator,
and Fd is the fractional-division frequency.
PHASE DETECTOR
The 1-MHz reference signal from divide-by-10 U37, and the 1-MHz signal from the
N-divider U62 are connected to a digital phase-frequency detector (U30, U31, U32). If
the N-divider output frequency is less than the reference frequency, TP25 is low, and
the voltage at the output of level shifter Q17 is below ground. This results in turning off
CR18 and allowing current from U63 to flow through CR18 out of the integrator. This
raises the voltage at the output of the integrator, which raises the VCO frequency.
Similarly, if the N-divider output frequency is above the reference, TP24 is high
turning on CR16 and allowing current to flow through R97 into the integrator. This
lowers the voltage at the output of the integrator, which lowers the VCO frequency. If
the phase between the reference and N-divider output slips more than two cycles in
either direction, the corresponding phase-detector output is high or low. This provides
twice the integrator current during acquisition as a conventional phase-frequency
detector.
R51 provides a small bias current to the integrator to bias the phase detector in the
linear region; consequently, the up-pump is always on.
During calibration of the VCO, the Kv, the VCO gain coefficient is measured at many
frequencies across the band, and compensation data is stored in non-volatile memory.
The instrument software uses this data along with N to control the PLL bandwidth.
The PLL bandwidth is controlled by changing the current to the up-pump via KN
DAC (U7A, U6A), and the voltage-to-current converter, U62 and Q12.
6C-8