Fluke 6080A Service Manual page 121

Memory Control
Decoder PAL U11 decodes the memory selects and contains additional write
protection logic for the the calibration/compensation memory and the instrument
states stored in the battery-backed RAM. Timing PAL U15 adds one wait state to each
memory read or write cycle.
Individual upper-byte and lower-byte read and write enable signals are generated from
68HCOOO control signals R / W , UDS, and LDS by U22. Signals RDU and RDL are
read enables for the upper-byte and lower-byte respectively. Signals WRU and WRL
are write enables for the upper-byte and lower-byte respectively.
Front Panel Interface
Data is transferred to and from the front panel circuitry through tri-state bidirectional
data buffer U31. The corresponding address signals are transferred through tri-state
buffer U32. These buffers are active when a front panel latch is addressed and the
buffer control signal from U43 is low. Otherwise, the buffer is in the high-impedance
state. To reduce RF emissions from the Generator, low-pass filters and bypass
capacitors are used on all data and select signals to the front panel.
The front panel interrupt rate is determined by the binary dividers U14 and U20. Under
normal operation, the system clock is divided by 8192 to generate a front panel
interrupt every 540 microseconds. When the display is blanked by special function, the
interrupt rate is divided by an additional factor of 32 to reduce the burden on the
microprocessor, thus reducing the software response time.
IEEE-488 Interface
All IEEE-488 communications are handled by U28, an NEC μPD7210 talker/listener
IC. The 7210 is connected directly to the system address and data bus and
communicates with the microprocessor as a memory mapped I/O device.
The active low interrupt signal IEINTL is connected to the level two interrupt on the
microprocessor. Tri-state bus drivers U29 and U30 interface the 7210 directly to the
IEEE-488 bus.
Attenuator Control Interface
The attenuator control signals are latched by U39. Darlington driver U40 provides the
level shifting necessary to control the A7 Relay Driver/RPP PCA.
Module I/O
Control data is transferred to the RF circuitry through two byte-wide unidirectional
data buses. Data is transferred to the upper module through J3 and to the lower
module through J6.
Select lines BSEL0L, BSEL1L, and BSEL5L, and address lines SAB2, SAB1, and
SAB0 are decoded into individual latch enables for the upper module on the A4
subsynthesizer PCA. Tri-state buffers U24 and U33 provide drive current when active
and allow these signals to float when inactive.
Select lines BSEL2L, BSEL3L, and BSEL4L and address lines BAB2, BAB1, and
BAB0 are decoded into individual latch enables for the lower module on the A11
Modulation Control PCA. Tri-state buffers U25 and U27 provide drive current when
active and allow these signals to float when inactive.
TROUBLESHOOTING AND REPAIR
DIGITAL CONTROLLER
6B-5.
6B-6.
6B-7.
6B-8.
6B-9.
6B-3