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Testing Performance
To test the multiple-clock, multiple-edge, state acquisition
Select the clocks to be tested.
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a Touch the clock field to be tested and then select the following combination of clock
edges: J↓ + K↓ + L↓ + M↓.
b Touch Done to exit the Master Clock menu.
In the logic analyzer Format menu, touch Run. The display should show an
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alternating pattern of AA and 55. If the "Search Failed" yellow bar message does not
appear, the test passes. Record the Pass or Fail results in the performance test
record.
Test the next setup/hold combination.
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a In the logic analyzer Format menu, touch Master Clock.
b Turn off the clocks just tested.
c Repeat steps 1 through 10 for the next setup/hold combination listed in step 1 on
page 3-37, until all listed setup/hold combinations have been tested.
When aligning the data and clock waveforms using the oscilloscope, align the waveforms
according to the setup time of the setup/hold combination being tested, +0.0 ps or −100 ps.
3–40
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