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Specifications
The specifications are the performance standards against which the product is tested.
Minimum State Clock Pulse Width
Threshold Accuracy
Clock Scheme:
Single Clock, Single Edge:
1
Setup/Hold Time:
Maximum State Speed
Minimum Master-to-Master Clock Time
Single Clock, Multiple Edges:
1
Setup/Hold Time:
Maximum State Speed
Minimum Master-to-Master Clock Time
Multiple Clocks, Multiple Edges:
1
Setup/Hold Time:
Maximum State Speed
Minimum Master-to-Master Clock Time
1
Specified for an input signal VH = −0.9 V, VL = −1.7 V, and threshold = −1.3 V.
2
An HP 16555A in an HP 16500B mainframe using operating system v2.xx has maximum state speed of 100 MHz and minimum
Master-to-Master Clock Time of 10.0 ns for single-clock, single-edge clocking. 110-MHz single-clock state acquisition mode is
available with HP 16500B mainframe operating system v3.00 or higher or HP 16500C mainframe operating system v1.00 or higher
(refer to "Operating System"). The maximum state acquisition speed is 100 MHz for all other clocking modes.
1
3.5 ns
± (100 mV + 3% of threshold setting)
0.0/3.5 ns through 3.5/0.0 ns,
adjustable in 500-ps increments
2
110 MHz
1
2
9.09 ns
0.0/4.0 ns through 4.0/0.0 ns,
adjustable in 500-ps increments
100 MHz
1
10.0 ns
0.0/4.5 ns through 4.5/0.0 ns,
adjustable in 500-ps increments
100 MHz
1
10.0 ns
General Information
Specifications
1–3
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